Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	274111	0	0
entropy_period_rd_A	2147483647	2884	0	0
intr_enable_rd_A	2147483647	3849	0	0
prefix_0_rd_A	2147483647	2885	0	0
prefix_10_rd_A	2147483647	3004	0	0
prefix_1_rd_A	2147483647	2778	0	0
prefix_2_rd_A	2147483647	2808	0	0
prefix_3_rd_A	2147483647	2830	0	0
prefix_4_rd_A	2147483647	2937	0	0
prefix_5_rd_A	2147483647	2738	0	0
prefix_6_rd_A	2147483647	3144	0	0
prefix_7_rd_A	2147483647	2747	0	0
prefix_8_rd_A	2147483647	2947	0	0
prefix_9_rd_A	2147483647	2962	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	274111	0	0
T24	63490	0	0	0
T29	655765	96335	0	0
T51	0	14680	0	0
T52	0	68397	0	0
T61	60566	0	0	0
T110	126440	0	0	0
T114	0	1	0	0
T122	0	9588	0	0
T123	0	82362	0	0
T124	0	134	0	0
T125	0	4	0	0
T126	0	3	0	0
T127	0	1	0	0
T128	25625	0	0	0
T129	266560	0	0	0
T130	643271	0	0	0
T131	967691	0	0	0
T132	436790	0	0	0
T133	339695	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2884	0	0
T99	4695	12	0	0
T103	13900	79	0	0
T115	31689	81	0	0
T126	4242	15	0	0
T127	4544	8	0	0
T142	26581	210	0	0
T143	145763	238	0	0
T144	6341	25	0	0
T145	6188	23	0	0
T146	126203	131	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3849	0	0
T99	4695	26	0	0
T103	13900	134	0	0
T115	31689	98	0	0
T118	1127	18	0	0
T126	4242	1	0	0
T127	4544	8	0	0
T142	26581	197	0	0
T143	145763	399	0	0
T144	6341	9	0	0
T147	1127	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2885	0	0
T99	4695	18	0	0
T103	13900	48	0	0
T115	31689	34	0	0
T126	4242	19	0	0
T127	4544	8	0	0
T142	26581	232	0	0
T143	145763	431	0	0
T144	6341	12	0	0
T145	6188	27	0	0
T146	126203	268	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3004	0	0
T99	4695	11	0	0
T103	13900	63	0	0
T115	31689	37	0	0
T126	4242	6	0	0
T127	4544	3	0	0
T142	26581	182	0	0
T143	145763	468	0	0
T144	6341	26	0	0
T145	6188	13	0	0
T146	126203	281	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2778	0	0
T99	4695	15	0	0
T103	13900	66	0	0
T115	31689	35	0	0
T126	4242	3	0	0
T127	4544	13	0	0
T142	26581	195	0	0
T143	145763	476	0	0
T144	6341	54	0	0
T145	6188	23	0	0
T146	126203	256	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2808	0	0
T99	4695	19	0	0
T103	13900	51	0	0
T115	31689	42	0	0
T126	4242	12	0	0
T127	4544	2	0	0
T142	26581	199	0	0
T143	145763	500	0	0
T144	6341	22	0	0
T145	6188	9	0	0
T146	126203	248	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2830	0	0
T99	4695	10	0	0
T103	13900	77	0	0
T115	31689	51	0	0
T126	4242	1	0	0
T142	26581	181	0	0
T143	145763	476	0	0
T144	6341	31	0	0
T145	6188	6	0	0
T146	126203	221	0	0
T148	7832	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2937	0	0
T99	4695	12	0	0
T103	13900	82	0	0
T115	31689	40	0	0
T126	4242	10	0	0
T127	4544	6	0	0
T142	26581	232	0	0
T143	145763	472	0	0
T144	6341	28	0	0
T145	6188	32	0	0
T146	126203	228	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2738	0	0
T99	4695	15	0	0
T103	13900	42	0	0
T115	31689	60	0	0
T126	4242	13	0	0
T127	4544	2	0	0
T142	26581	174	0	0
T143	145763	445	0	0
T144	6341	32	0	0
T145	6188	4	0	0
T146	126203	225	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3144	0	0
T99	4695	19	0	0
T103	13900	51	0	0
T115	31689	38	0	0
T126	4242	4	0	0
T127	4544	5	0	0
T142	26581	253	0	0
T143	145763	513	0	0
T144	6341	25	0	0
T145	6188	28	0	0
T146	126203	309	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2747	0	0
T99	4695	25	0	0
T103	13900	49	0	0
T115	31689	13	0	0
T126	4242	18	0	0
T127	4544	4	0	0
T142	26581	244	0	0
T143	145763	443	0	0
T144	6341	15	0	0
T145	6188	11	0	0
T146	126203	161	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2947	0	0
T99	4695	21	0	0
T103	13900	70	0	0
T115	31689	48	0	0
T126	4242	7	0	0
T127	4544	9	0	0
T142	26581	206	0	0
T143	145763	444	0	0
T144	6341	31	0	0
T145	6188	24	0	0
T146	126203	265	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2962	0	0
T99	4695	21	0	0
T103	13900	63	0	0
T115	31689	38	0	0
T124	7905	8	0	0
T126	4242	9	0	0
T127	4544	6	0	0
T142	26581	238	0	0
T143	145763	477	0	0
T144	6341	6	0	0
T145	6188	20	0	0