Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256281826

1

T1

5236

T2

93894

T3

6

full_word

200280599

1

T1

8331

T2

167996

T3

53

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456562175	1			T1	13567		T2	261890		T3	59
auto[TlIntgErrCmd]	80	1			T115	2		T116	4		T117	2
auto[TlIntgErrData]	78	1			T115	4		T116	1		T117	3
auto[TlIntgErrBoth]	92	1			T115	4		T116	5		T117	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240371132

1

T1

9528

T2

174259

T3

5

auto[1]

216191293

1

T1

4039

T2

87631

T3

54

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153170315	1			T1	3367		T2	57132		T3	3
auto[TlIntgErrNone]	partial	auto[1]	103111273	1			T1	1869		T2	36762		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	87200700	1			T1	6161		T2	117127		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	113079887	1			T1	2170		T2	50869		T3	51
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T115	1		T116	3		T117	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T115	1		T116	1		T169	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T170	1		T171	1		-	-
auto[TlIntgErrData]	partial	auto[0]	33	1			T115	2		T169	1		T172	4
auto[TlIntgErrData]	partial	auto[1]	40	1			T115	1		T116	1		T117	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T115	1		T173	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T173	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T115	1		T116	2		T169	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T115	2		T116	3		T117	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T115	1		T117	1		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T171	1		-	-		-	-