Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	319782	0	0
entropy_period_rd_A	2147483647	1629	0	0
intr_enable_rd_A	2147483647	2518	0	0
prefix_0_rd_A	2147483647	2003	0	0
prefix_10_rd_A	2147483647	2131	0	0
prefix_1_rd_A	2147483647	2117	0	0
prefix_2_rd_A	2147483647	2072	0	0
prefix_3_rd_A	2147483647	2004	0	0
prefix_4_rd_A	2147483647	2005	0	0
prefix_5_rd_A	2147483647	1990	0	0
prefix_6_rd_A	2147483647	2113	0	0
prefix_7_rd_A	2147483647	2090	0	0
prefix_8_rd_A	2147483647	1980	0	0
prefix_9_rd_A	2147483647	2087	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319782	0	0
T44	271815	39287	0	0
T45	926917	0	0	0
T48	817947	0	0	0
T51	1075	0	0	0
T53	0	22513	0	0
T54	0	33787	0	0
T64	72081	0	0	0
T115	0	3	0	0
T121	0	18550	0	0
T122	0	54460	0	0
T123	0	47730	0	0
T124	0	100919	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	43814	0	0	0
T128	149792	0	0	0
T129	655917	0	0	0
T130	17800	0	0	0
T131	202615	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1629	0	0
T91	8056	30	0	0
T108	3259	5	0	0
T126	3985	5	0	0
T144	9887	16	0	0
T145	2164	7	0	0
T146	52597	426	0	0
T147	4482	12	0	0
T148	2452	11	0	0
T149	26240	226	0	0
T150	4416	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2518	0	0
T91	8056	43	0	0
T118	1564	32	0	0
T119	1931	23	0	0
T120	1572	28	0	0
T126	3985	11	0	0
T144	9887	14	0	0
T145	2164	1	0	0
T146	52597	458	0	0
T151	1201	21	0	0
T152	1512	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2003	0	0
T91	8056	26	0	0
T108	3259	4	0	0
T126	3985	8	0	0
T144	9887	39	0	0
T145	2164	2	0	0
T146	52597	417	0	0
T147	4482	3	0	0
T148	2452	12	0	0
T149	26240	228	0	0
T150	4416	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2131	0	0
T91	8056	17	0	0
T108	3259	12	0	0
T126	3985	11	0	0
T144	9887	35	0	0
T145	2164	5	0	0
T146	52597	425	0	0
T147	4482	2	0	0
T148	2452	12	0	0
T149	26240	205	0	0
T150	4416	14	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T91	8056	29	0	0
T126	3985	9	0	0
T144	9887	30	0	0
T145	2164	7	0	0
T146	52597	415	0	0
T147	4482	9	0	0
T148	2452	13	0	0
T149	26240	198	0	0
T150	4416	7	0	0
T153	5861	39	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2072	0	0
T91	8056	24	0	0
T108	3259	8	0	0
T126	3985	6	0	0
T144	9887	9	0	0
T145	2164	7	0	0
T146	52597	407	0	0
T147	4482	9	0	0
T148	2452	19	0	0
T149	26240	218	0	0
T150	4416	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2004	0	0
T91	8056	19	0	0
T108	3259	8	0	0
T126	3985	8	0	0
T144	9887	55	0	0
T145	2164	2	0	0
T146	52597	418	0	0
T147	4482	7	0	0
T148	2452	1	0	0
T149	26240	215	0	0
T150	4416	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2005	0	0
T91	8056	16	0	0
T108	3259	6	0	0
T126	3985	9	0	0
T144	9887	25	0	0
T145	2164	2	0	0
T146	52597	440	0	0
T147	4482	3	0	0
T148	2452	15	0	0
T149	26240	219	0	0
T150	4416	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T91	8056	31	0	0
T108	3259	13	0	0
T126	3985	3	0	0
T144	9887	9	0	0
T145	2164	2	0	0
T146	52597	429	0	0
T147	4482	7	0	0
T148	2452	13	0	0
T149	26240	209	0	0
T150	4416	13	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2113	0	0
T91	8056	37	0	0
T108	3259	7	0	0
T126	3985	6	0	0
T144	9887	31	0	0
T145	2164	6	0	0
T146	52597	445	0	0
T147	4482	3	0	0
T148	2452	15	0	0
T149	26240	196	0	0
T150	4416	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2090	0	0
T91	8056	29	0	0
T108	3259	16	0	0
T126	3985	9	0	0
T145	2164	8	0	0
T146	52597	457	0	0
T147	4482	3	0	0
T148	2452	6	0	0
T149	26240	217	0	0
T150	4416	2	0	0
T153	5861	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1980	0	0
T91	8056	15	0	0
T108	3259	8	0	0
T126	3985	10	0	0
T144	9887	18	0	0
T145	2164	5	0	0
T146	52597	403	0	0
T147	4482	11	0	0
T148	2452	5	0	0
T149	26240	194	0	0
T154	4943	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2087	0	0
T91	8056	20	0	0
T108	3259	9	0	0
T126	3985	9	0	0
T144	9887	22	0	0
T145	2164	3	0	0
T146	52597	446	0	0
T147	4482	11	0	0
T148	2452	7	0	0
T149	26240	214	0	0
T150	4416	6	0	0