Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255485655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

201559816

1

T1

340206

T2

261812

T3

359522

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	241317434	1			T1	437239		T2	336447		T3	459219
values[0x0]	103666015	1			T1	200547		T2	153835		T3	212236
values[0x1]	112062022	1			T1	218255		T2	166063		T3	228119

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199158323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

257887148

1

T1

452239

T2

348229

T3

476178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1326747	1			T1	3235		T2	2614		T3	3486
valid_sources[0x01]	1325698	1			T1	3314		T2	2570		T3	3455
valid_sources[0x02]	1321228	1			T1	3370		T2	2528		T3	3536
valid_sources[0x03]	1327365	1			T1	3331		T2	2582		T3	3479
valid_sources[0x04]	1328532	1			T1	3302		T2	2521		T3	3551
valid_sources[0x05]	1811920	1			T1	3363		T2	2535		T3	3589
valid_sources[0x06]	1317196	1			T1	3289		T2	2680		T3	3536
valid_sources[0x07]	1971003	1			T1	3388		T2	2587		T3	3523
valid_sources[0x08]	3451334	1			T1	3362		T2	2537		T3	3535
valid_sources[0x09]	1592894	1			T1	3384		T2	2561		T3	3445
valid_sources[0x0a]	2772746	1			T1	3391		T2	2483		T3	3524
valid_sources[0x0b]	1326208	1			T1	3360		T2	2542		T3	3569
valid_sources[0x0c]	1324478	1			T1	3272		T2	2609		T3	3515
valid_sources[0x0d]	1325510	1			T1	3189		T2	2633		T3	3471
valid_sources[0x0e]	1334335	1			T1	3380		T2	2548		T3	3631
valid_sources[0x0f]	1323785	1			T1	3499		T2	2519		T3	3539
valid_sources[0x10]	1483214	1			T1	3374		T2	2543		T3	3482
valid_sources[0x11]	1326116	1			T1	3259		T2	2614		T3	3485
valid_sources[0x12]	2355216	1			T1	3334		T2	2512		T3	3538
valid_sources[0x13]	1342617	1			T1	3344		T2	2500		T3	3500
valid_sources[0x14]	1324900	1			T1	3237		T2	2697		T3	3564
valid_sources[0x15]	1325141	1			T1	3408		T2	2512		T3	3550
valid_sources[0x16]	3607435	1			T1	3355		T2	2674		T3	3426
valid_sources[0x17]	1322565	1			T1	3345		T2	2562		T3	3479
valid_sources[0x18]	2189219	1			T1	3307		T2	2540		T3	3593
valid_sources[0x19]	1910905	1			T1	3414		T2	2615		T3	3497
valid_sources[0x1a]	1323205	1			T1	3333		T2	2436		T3	3481
valid_sources[0x1b]	2047839	1			T1	3412		T2	2499		T3	3497
valid_sources[0x1c]	1956290	1			T1	3288		T2	2631		T3	3570
valid_sources[0x1d]	1332702	1			T1	3300		T2	2494		T3	3506
valid_sources[0x1e]	1321615	1			T1	3347		T2	2529		T3	3529
valid_sources[0x1f]	1338260	1			T1	3338		T2	2574		T3	3604
valid_sources[0x20]	4542554	1			T1	3361		T2	2549		T3	3535
valid_sources[0x21]	4411411	1			T1	3287		T2	2507		T3	3414
valid_sources[0x22]	1323747	1			T1	3366		T2	2646		T3	3555
valid_sources[0x23]	3388175	1			T1	3217		T2	2593		T3	3463
valid_sources[0x24]	1324039	1			T1	3366		T2	2588		T3	3498
valid_sources[0x25]	1327414	1			T1	3420		T2	2430		T3	3508
valid_sources[0x26]	2331702	1			T1	3334		T2	2524		T3	3360
valid_sources[0x27]	1364183	1			T1	3320		T2	2492		T3	3483
valid_sources[0x28]	1319901	1			T1	3366		T2	2613		T3	3409
valid_sources[0x29]	1321043	1			T1	3287		T2	2533		T3	3536
valid_sources[0x2a]	1335776	1			T1	3404		T2	2595		T3	3623
valid_sources[0x2b]	1813729	1			T1	3362		T2	2604		T3	3550
valid_sources[0x2c]	1326881	1			T1	3355		T2	2643		T3	3595
valid_sources[0x2d]	2197779	1			T1	3404		T2	2564		T3	3474
valid_sources[0x2e]	1320740	1			T1	3287		T2	2609		T3	3481
valid_sources[0x2f]	1322621	1			T1	3266		T2	2571		T3	3491
valid_sources[0x30]	1320366	1			T1	3308		T2	2635		T3	3583
valid_sources[0x31]	1321804	1			T1	3438		T2	2598		T3	3490
valid_sources[0x32]	1314254	1			T1	3369		T2	2634		T3	3430
valid_sources[0x33]	1332634	1			T1	3356		T2	2545		T3	3369
valid_sources[0x34]	2247672	1			T1	3323		T2	2530		T3	3543
valid_sources[0x35]	1321816	1			T1	3341		T2	2482		T3	3524
valid_sources[0x36]	2232982	1			T1	3368		T2	2564		T3	3450
valid_sources[0x37]	1334155	1			T1	3377		T2	2510		T3	3583
valid_sources[0x38]	1323338	1			T1	3369		T2	2558		T3	3563
valid_sources[0x39]	2515104	1			T1	3435		T2	2476		T3	3530
valid_sources[0x3a]	1318753	1			T1	3291		T2	2615		T3	3582
valid_sources[0x3b]	1324976	1			T1	3350		T2	2521		T3	3566
valid_sources[0x3c]	5367622	1			T1	3434		T2	2610		T3	3500
valid_sources[0x3d]	1329071	1			T1	3372		T2	2558		T3	3461
valid_sources[0x3e]	1396147	1			T1	3261		T2	2610		T3	3510
valid_sources[0x3f]	1402982	1			T1	3318		T2	2693		T3	3598
valid_sources[0x40]	4208276	1			T1	3349		T2	2524		T3	3563
valid_sources[0x41]	1327598	1			T1	3311		T2	2509		T3	3634
valid_sources[0x42]	1858928	1			T1	3524		T2	2616		T3	3553
valid_sources[0x43]	2204495	1			T1	3417		T2	2573		T3	3533
valid_sources[0x44]	1316336	1			T1	3326		T2	2633		T3	3559
valid_sources[0x45]	1324520	1			T1	3320		T2	2575		T3	3509
valid_sources[0x46]	1320986	1			T1	3377		T2	2421		T3	3373
valid_sources[0x47]	1787058	1			T1	3326		T2	2557		T3	3434
valid_sources[0x48]	1323718	1			T1	3388		T2	2577		T3	3499
valid_sources[0x49]	1319690	1			T1	3257		T2	2576		T3	3396
valid_sources[0x4a]	1329855	1			T1	3348		T2	2615		T3	3576
valid_sources[0x4b]	1319524	1			T1	3386		T2	2526		T3	3582
valid_sources[0x4c]	1326060	1			T1	3433		T2	2642		T3	3592
valid_sources[0x4d]	1345435	1			T1	3458		T2	2614		T3	3417
valid_sources[0x4e]	3384592	1			T1	3251		T2	2617		T3	3563
valid_sources[0x4f]	1317504	1			T1	3451		T2	2738		T3	3554
valid_sources[0x50]	1321874	1			T1	3394		T2	2608		T3	3410
valid_sources[0x51]	1325217	1			T1	3419		T2	2499		T3	3518
valid_sources[0x52]	1323130	1			T1	3383		T2	2555		T3	3660
valid_sources[0x53]	1335261	1			T1	3368		T2	2458		T3	3493
valid_sources[0x54]	3743925	1			T1	3375		T2	2524		T3	3410
valid_sources[0x55]	1323123	1			T1	3284		T2	2569		T3	3632
valid_sources[0x56]	3473200	1			T1	3392		T2	2685		T3	3551
valid_sources[0x57]	2069119	1			T1	3345		T2	2569		T3	3486
valid_sources[0x58]	3365999	1			T1	3441		T2	2639		T3	3579
valid_sources[0x59]	1324571	1			T1	3296		T2	2514		T3	3504
valid_sources[0x5a]	1320622	1			T1	3432		T2	2525		T3	3597
valid_sources[0x5b]	1322643	1			T1	3363		T2	2539		T3	3588
valid_sources[0x5c]	1618780	1			T1	3286		T2	2641		T3	3581
valid_sources[0x5d]	2238895	1			T1	3436		T2	2620		T3	3521
valid_sources[0x5e]	1986168	1			T1	3340		T2	2647		T3	3572
valid_sources[0x5f]	1811579	1			T1	3368		T2	2600		T3	3428
valid_sources[0x60]	1986299	1			T1	3262		T2	2509		T3	3473
valid_sources[0x61]	1856558	1			T1	3375		T2	2620		T3	3447
valid_sources[0x62]	1353550	1			T1	3317		T2	2570		T3	3540
valid_sources[0x63]	1395749	1			T1	3290		T2	2567		T3	3522
valid_sources[0x64]	1325537	1			T1	3341		T2	2620		T3	3504
valid_sources[0x65]	1321021	1			T1	3397		T2	2539		T3	3452
valid_sources[0x66]	1324462	1			T1	3402		T2	2590		T3	3524
valid_sources[0x67]	1316042	1			T1	3286		T2	2491		T3	3494
valid_sources[0x68]	1328487	1			T1	3425		T2	2615		T3	3461
valid_sources[0x69]	1318746	1			T1	3351		T2	2654		T3	3469
valid_sources[0x6a]	1790006	1			T1	3317		T2	2559		T3	3519
valid_sources[0x6b]	1381998	1			T1	3387		T2	2615		T3	3476
valid_sources[0x6c]	1324364	1			T1	3392		T2	2498		T3	3573
valid_sources[0x6d]	1388295	1			T1	3293		T2	2578		T3	3497
valid_sources[0x6e]	1325381	1			T1	3269		T2	2608		T3	3404
valid_sources[0x6f]	1962071	1			T1	3324		T2	2486		T3	3515
valid_sources[0x70]	2255110	1			T1	3225		T2	2520		T3	3605
valid_sources[0x71]	1315871	1			T1	3416		T2	2509		T3	3564
valid_sources[0x72]	1957981	1			T1	3432		T2	2542		T3	3457
valid_sources[0x73]	1321606	1			T1	3343		T2	2585		T3	3567
valid_sources[0x74]	1332011	1			T1	3212		T2	2496		T3	3674
valid_sources[0x75]	1321801	1			T1	3497		T2	2562		T3	3510
valid_sources[0x76]	1452883	1			T1	3273		T2	2558		T3	3381
valid_sources[0x77]	1320841	1			T1	3328		T2	2534		T3	3575
valid_sources[0x78]	1331492	1			T1	3246		T2	2652		T3	3518
valid_sources[0x79]	1326173	1			T1	3352		T2	2521		T3	3425
valid_sources[0x7a]	1347274	1			T1	3379		T2	2583		T3	3545
valid_sources[0x7b]	1329575	1			T1	3233		T2	2591		T3	3523
valid_sources[0x7c]	1494938	1			T1	3278		T2	2455		T3	3437
valid_sources[0x7d]	4689821	1			T1	3333		T2	2526		T3	3527
valid_sources[0x7e]	1324847	1			T1	3384		T2	2503		T3	3602
valid_sources[0x7f]	3288685	1			T1	3265		T2	2573		T3	3449
valid_sources[0x80]	2494418	1			T1	3358		T2	2600		T3	3614

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87938012

1

T1

126186

T2

99028

T3

131847

values[0x0]

all_enables

biggest_size

61105728

1

T1

115043

T2

88397

T3

123178

values[0x1]

all_enables

biggest_size

52516076

1

T1

98977

T2

74387

T3

104497