Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256787066

1

T1

515835

T2

394533

T3

540052

full_word

201641573

1

T1

340206

T2

261812

T3

359522

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458428309	1			T1	856041		T2	656345		T3	899574
auto[TlIntgErrCmd]	97	1			T135	2		T136	4		T137	7
auto[TlIntgErrData]	112	1			T135	5		T136	3		T137	6
auto[TlIntgErrBoth]	121	1			T135	3		T136	13		T137	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241563250

1

T1

437239

T2

336447

T3

459219

auto[1]

216865389

1

T1

418802

T2

319898

T3

440355

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153605117	1			T1	311053		T2	237419		T3	327372
auto[TlIntgErrNone]	partial	auto[1]	103181643	1			T1	204782		T2	157114		T3	212680
auto[TlIntgErrNone]	full_word	auto[0]	87957979	1			T1	126186		T2	99028		T3	131847
auto[TlIntgErrNone]	full_word	auto[1]	113683570	1			T1	214020		T2	162784		T3	227675
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T135	1		T136	3		T163	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T135	1		T136	1		T137	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T206	1		T205	1		T207	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T163	1		T164	1		T208	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T135	1		T136	2		T137	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T135	3		T136	1		T137	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T135	1		T208	1		T204	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T202	2		T209	1		T206	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T135	1		T136	6		T137	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T135	2		T136	6		T137	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T163	1		T208	1		T204	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T136	1		T208	1		T210	1