Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253921880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199944693

1

T1

100219

T2

26229

T3

97236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239820109	1			T1	127005		T2	28061		T3	103055
values[0x0]	102779232	1			T1	549948		T2	6655		T3	23680
values[0x1]	111267232	1			T1	596200		T2	7142		T3	25045

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197878449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

255988124

1

T1

131276

T2

29855

T3

109467

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1276388	1			T1	9482		T2	158		T3	39
valid_sources[0x01]	1451921	1			T1	9275		T2	153		T3	34
valid_sources[0x02]	1274903	1			T1	9417		T2	210		T3	33
valid_sources[0x03]	1274020	1			T1	9405		T2	185		T3	33
valid_sources[0x04]	2137672	1			T1	9199		T2	172		T3	44
valid_sources[0x05]	1341466	1			T1	9238		T2	145		T3	28
valid_sources[0x06]	1288902	1			T1	9498		T2	148		T3	38
valid_sources[0x07]	1303209	1			T1	9496		T2	196		T3	34
valid_sources[0x08]	1273835	1			T1	9370		T2	141		T3	30
valid_sources[0x09]	1466353	1			T1	9336		T2	142		T3	40
valid_sources[0x0a]	3668782	1			T1	9669		T2	168		T3	32
valid_sources[0x0b]	1354801	1			T1	9436		T2	179		T3	33
valid_sources[0x0c]	1269000	1			T1	9360		T2	140		T3	35
valid_sources[0x0d]	1316755	1			T1	9298		T2	122		T3	24
valid_sources[0x0e]	2278611	1			T1	9534		T2	183		T3	142924
valid_sources[0x0f]	1956098	1			T1	9243		T2	197		T3	36
valid_sources[0x10]	1407600	1			T1	9301		T2	126		T3	29
valid_sources[0x11]	1288664	1			T1	9466		T2	151		T3	31
valid_sources[0x12]	1274045	1			T1	9570		T2	161		T3	28
valid_sources[0x13]	3669917	1			T1	9331		T2	139		T3	33
valid_sources[0x14]	3826637	1			T1	9436		T2	102		T3	32
valid_sources[0x15]	2180863	1			T1	9537		T2	212		T3	20
valid_sources[0x16]	2819925	1			T1	9544		T2	143		T3	42
valid_sources[0x17]	1944903	1			T1	9391		T2	155		T3	47
valid_sources[0x18]	2071485	1			T1	9428		T2	150		T3	23
valid_sources[0x19]	1275356	1			T1	9337		T2	133		T3	41
valid_sources[0x1a]	1273135	1			T1	9433		T2	153		T3	27
valid_sources[0x1b]	1324750	1			T1	9508		T2	106		T3	31
valid_sources[0x1c]	1271733	1			T1	9281		T2	109		T3	47
valid_sources[0x1d]	2272603	1			T1	9750		T2	136		T3	36
valid_sources[0x1e]	1276231	1			T1	9173		T2	169		T3	30
valid_sources[0x1f]	1272493	1			T1	9648		T2	193		T3	34
valid_sources[0x20]	1734535	1			T1	9345		T2	194		T3	36
valid_sources[0x21]	1276139	1			T1	9606		T2	157		T3	41
valid_sources[0x22]	1273433	1			T1	9607		T2	197		T3	31
valid_sources[0x23]	1273353	1			T1	9210		T2	140		T3	49
valid_sources[0x24]	1292626	1			T1	9369		T2	190		T3	31
valid_sources[0x25]	2196227	1			T1	9421		T2	177		T3	42
valid_sources[0x26]	1287737	1			T1	9376		T2	177		T3	30
valid_sources[0x27]	1653601	1			T1	9276		T2	176		T3	35
valid_sources[0x28]	1463354	1			T1	9468		T2	146		T3	23
valid_sources[0x29]	1273096	1			T1	9470		T2	170		T3	34
valid_sources[0x2a]	1428957	1			T1	9436		T2	231		T3	50
valid_sources[0x2b]	1565762	1			T1	9391		T2	146		T3	33
valid_sources[0x2c]	3658242	1			T1	9460		T2	137		T3	26
valid_sources[0x2d]	2530483	1			T1	9739		T2	158		T3	31
valid_sources[0x2e]	1271021	1			T1	9204		T2	142		T3	38
valid_sources[0x2f]	1355487	1			T1	9386		T2	203		T3	34
valid_sources[0x30]	1275885	1			T1	9383		T2	178		T3	42
valid_sources[0x31]	1275071	1			T1	9551		T2	176		T3	39
valid_sources[0x32]	2232919	1			T1	9341		T2	100		T3	35
valid_sources[0x33]	1275880	1			T1	9297		T2	162		T3	35
valid_sources[0x34]	3738002	1			T1	9423		T2	180		T3	38
valid_sources[0x35]	2514365	1			T1	9448		T2	151		T3	33
valid_sources[0x36]	3713048	1			T1	9313		T2	157		T3	39
valid_sources[0x37]	2048160	1			T1	9318		T2	200		T3	38
valid_sources[0x38]	1268655	1			T1	9574		T2	229		T3	35
valid_sources[0x39]	2056991	1			T1	9603		T2	137		T3	31
valid_sources[0x3a]	1428528	1			T1	9116		T2	178		T3	30
valid_sources[0x3b]	1410967	1			T1	9269		T2	166		T3	25
valid_sources[0x3c]	1287526	1			T1	9484		T2	147		T3	31
valid_sources[0x3d]	1748914	1			T1	9524		T2	143		T3	39
valid_sources[0x3e]	1536941	1			T1	9388		T2	176		T3	35
valid_sources[0x3f]	1286738	1			T1	9308		T2	210		T3	43
valid_sources[0x40]	2203119	1			T1	9632		T2	121		T3	34
valid_sources[0x41]	1283516	1			T1	9497		T2	181		T3	41
valid_sources[0x42]	1271661	1			T1	9294		T2	168		T3	39
valid_sources[0x43]	1277434	1			T1	9502		T2	161		T3	37
valid_sources[0x44]	1273483	1			T1	9215		T2	147		T3	44
valid_sources[0x45]	1273784	1			T1	9440		T2	237		T3	37
valid_sources[0x46]	3326302	1			T1	9588		T2	136		T3	42
valid_sources[0x47]	3707150	1			T1	9462		T2	178		T3	27
valid_sources[0x48]	1439757	1			T1	9430		T2	149		T3	36
valid_sources[0x49]	3499161	1			T1	9270		T2	181		T3	37
valid_sources[0x4a]	4204756	1			T1	9783		T2	141		T3	29
valid_sources[0x4b]	1274987	1			T1	9073		T2	175		T3	43
valid_sources[0x4c]	3317027	1			T1	9570		T2	167		T3	32
valid_sources[0x4d]	3667187	1			T1	9404		T2	124		T3	31
valid_sources[0x4e]	1987057	1			T1	9307		T2	197		T3	27
valid_sources[0x4f]	1420463	1			T1	9703		T2	107		T3	39
valid_sources[0x50]	1278891	1			T1	9537		T2	152		T3	38
valid_sources[0x51]	1276582	1			T1	9239		T2	116		T3	43
valid_sources[0x52]	1644491	1			T1	9223		T2	132		T3	40
valid_sources[0x53]	1271977	1			T1	9357		T2	130		T3	37
valid_sources[0x54]	4645778	1			T1	9341		T2	167		T3	32
valid_sources[0x55]	1274815	1			T1	9571		T2	138		T3	27
valid_sources[0x56]	1932581	1			T1	9441		T2	166		T3	32
valid_sources[0x57]	4066724	1			T1	9494		T2	157		T3	37
valid_sources[0x58]	1288692	1			T1	9844		T2	200		T3	28
valid_sources[0x59]	2597010	1			T1	9549		T2	193		T3	31
valid_sources[0x5a]	1273600	1			T1	9473		T2	124		T3	28
valid_sources[0x5b]	1273453	1			T1	9440		T2	180		T3	35
valid_sources[0x5c]	1275163	1			T1	9333		T2	107		T3	25
valid_sources[0x5d]	1306717	1			T1	9750		T2	146		T3	28
valid_sources[0x5e]	1457338	1			T1	9566		T2	153		T3	38
valid_sources[0x5f]	3723887	1			T1	9511		T2	130		T3	36
valid_sources[0x60]	1940094	1			T1	9250		T2	222		T3	43
valid_sources[0x61]	1275961	1			T1	9386		T2	171		T3	36
valid_sources[0x62]	1278002	1			T1	9571		T2	191		T3	30
valid_sources[0x63]	1273848	1			T1	9275		T2	127		T3	32
valid_sources[0x64]	1296663	1			T1	9647		T2	158		T3	41
valid_sources[0x65]	2139106	1			T1	9328		T2	164		T3	36
valid_sources[0x66]	1270689	1			T1	9210		T2	216		T3	49
valid_sources[0x67]	3037154	1			T1	9434		T2	224		T3	45
valid_sources[0x68]	1272637	1			T1	9427		T2	168		T3	32
valid_sources[0x69]	1583521	1			T1	9230		T2	138		T3	39
valid_sources[0x6a]	1271619	1			T1	9420		T2	164		T3	39
valid_sources[0x6b]	1273725	1			T1	9136		T2	141		T3	37
valid_sources[0x6c]	1341728	1			T1	9476		T2	227		T3	35
valid_sources[0x6d]	1266739	1			T1	9512		T2	142		T3	30
valid_sources[0x6e]	4248752	1			T1	9627		T2	195		T3	27
valid_sources[0x6f]	1280862	1			T1	9286		T2	171		T3	39
valid_sources[0x70]	1277305	1			T1	9431		T2	173		T3	32
valid_sources[0x71]	1268081	1			T1	9145		T2	250		T3	41
valid_sources[0x72]	3033636	1			T1	9427		T2	146		T3	44
valid_sources[0x73]	1281921	1			T1	9235		T2	161		T3	50
valid_sources[0x74]	1315097	1			T1	9557		T2	169		T3	37
valid_sources[0x75]	1729299	1			T1	9521		T2	170		T3	31
valid_sources[0x76]	1275531	1			T1	9554		T2	167		T3	35
valid_sources[0x77]	1296693	1			T1	9347		T2	71		T3	40
valid_sources[0x78]	1276923	1			T1	9300		T2	188		T3	38
valid_sources[0x79]	1275346	1			T1	9425		T2	137		T3	33
valid_sources[0x7a]	1274316	1			T1	9529		T2	162		T3	40
valid_sources[0x7b]	1744408	1			T1	9803		T2	181		T3	27
valid_sources[0x7c]	3688082	1			T1	9637		T2	131		T3	30
valid_sources[0x7d]	1777434	1			T1	9752		T2	171		T3	32
valid_sources[0x7e]	1280785	1			T1	9553		T2	160		T3	38
valid_sources[0x7f]	2189873	1			T1	9142		T2	184		T3	34
valid_sources[0x80]	1273503	1			T1	9764		T2	164		T3	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87597431

1

T1

426561

T2

18640

T3

69885

values[0x0]

all_enables

biggest_size

60446731

1

T1

312273

T2

4048

T3

14653

values[0x1]

all_enables

biggest_size

51900531

1

T1

263364

T2

3541

T3

12698