Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257038412

1

T1

141400

T2

15629

T3

54544

full_word

200139705

1

T1

100219

T2

26229

T3

97236

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	457177847	1			T1	241620		T2	41858		T3	151780
auto[TlIntgErrCmd]	81	1			T121	3		T122	3		T123	4
auto[TlIntgErrData]	85	1			T121	5		T122	1		T123	2
auto[TlIntgErrBoth]	104	1			T121	2		T122	6		T123	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240423477

1

T1

127005

T2

28061

T3

103055

auto[1]

216754640

1

T1

114614

T2

13797

T3

48725

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152776811	1			T1	843493		T2	9421		T3	33170
auto[TlIntgErrNone]	partial	auto[1]	104261354	1			T1	570511		T2	6208		T3	21374
auto[TlIntgErrNone]	full_word	auto[0]	87646547	1			T1	426561		T2	18640		T3	69885
auto[TlIntgErrNone]	full_word	auto[1]	112493135	1			T1	575637		T2	7589		T3	27351
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T122	2		T123	2		T183	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T121	3		T122	1		T123	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T184	1		T185	2		T127	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T121	2		T122	1		T123	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T121	2		T123	1		T183	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T186	1		T185	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T121	1		T153	2		T187	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T122	3		T123	2		T183	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T121	1		T122	3		T123	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T127	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T187	1		T189	1		T185	1