Unified Coverage Report :: Module :: sha3

Module : sha3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.32	97.56	88.89		81.82	93.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3	95.96	97.56	88.89		100.00	93.33	100.00

---

Module Instance : tb.dut.u_sha3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	97.56	88.89		100.00	93.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.16	91.91	88.51	100.00	80.56	92.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak	81.47	81.77	88.24	100.00	40.00	78.79	100.00
u_pad	96.28	99.42	88.37	100.00	94.12	95.79	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3

	Line No.	Total	Covered	Percent
TOTAL		82	80	97.56
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	5	5	100.00
ALWAYS	198	3	3	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	207	6	6	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	227	3	3	100.00
ALWAYS	237	38	38	100.00
ALWAYS	332	3	3	100.00
ALWAYS	349	12	10	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
144	1	1
148	1	1
172	1	1
173	1	1
178	1	1
179	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
198	2	2
199	1	1
203	1	1
207	2	2
208	2	2
209	1	1
210	1	1
			MISSING_ELSE
214	1	1
217	1	1
218	1	1
220	1	1
227	3	3
237	1	1
240	1	1
241	1	1
242	1	1
243	1	1
245	1	1
247	1	1
248	1	1
250	1	1
252	1	1
254	1	1
255	1	1
257	1	1
259	1	1
264	1	1
265	1	1
267	1	1
268	1	1
269	1	1
271	1	1
276	1	1
277	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
288	1	1
290	1	1
295	1	1
296	1	1
298	1	1
303	1	1
308	1	1
309	1	1
321	1	1
322	1	1
			MISSING_ELSE
332	1	1
333	1	1
334	1	1
349	1	1
351	1	1
353	1	1
355	1	1
			MISSING_ELSE
364	1	1
366	1	1
			MISSING_ELSE
375	1	1
376	0	1
			MISSING_ELSE
385	1	1
387	1	1
			MISSING_ELSE
396	1	1
398	0	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T10,T11,T12

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	9	81.82
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	255	Covered	T1,T2,T3
StFlush_sparse	286	Covered	T1,T2,T3
StIdle_sparse	259	Covered	T1,T2,T3
StManualRun_sparse	282	Covered	T2,T3,T15
StSqueeze_sparse	269	Covered	T1,T2,T3
StTerminalError_sparse	308	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StAbsorb_sparse->StSqueeze_sparse	269	Covered	T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse	322	Covered	T4,T5,T6
StFlush_sparse->StIdle_sparse	303	Covered	T1,T2,T3
StFlush_sparse->StTerminalError_sparse	322	Not Covered
StIdle_sparse->StAbsorb_sparse	255	Covered	T1,T2,T3
StIdle_sparse->StTerminalError_sparse	322	Covered	T10,T11,T12
StManualRun_sparse->StSqueeze_sparse	296	Covered	T2,T3,T15
StManualRun_sparse->StTerminalError_sparse	322	Not Covered
StSqueeze_sparse->StFlush_sparse	286	Covered	T1,T2,T3
StSqueeze_sparse->StManualRun_sparse	282	Covered	T2,T3,T15
StSqueeze_sparse->StTerminalError_sparse	322	Covered	T56

---

Branch Coverage for Module : sha3

	Line No.	Total	Covered	Percent
Branches		45	42	93.33
TERNARY	173	3	3	100.00
TERNARY	179	3	3	100.00
IF	184	2	2	100.00
IF	198	2	2	100.00
IF	207	4	4	100.00
IF	227	2	2	100.00
CASE	252	13	13	100.00
IF	321	2	2	100.00
CASE	332	3	2	66.67
CASE	351	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	173	((sha3pad_keccak_run || sw_keccak_run)) ? 
-2-:	173	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	179	(keccak_run) ? 
-2-:	179	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	198	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	207	if ((!rst_ni))
-2-:	208	if (process_i)
-3-:	209	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	case (st)
-2-:	254	if (start_i)
-3-:	264	if ((process_i && (!processing)))
-4-:	268	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	281	if (run_i)
-6-:	285	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	295	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle_sparse	0	-	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	1	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	1	-	-	Covered	T2,T3,T15
StSqueeze_sparse	-	-	-	0	1	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	0	0	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	-	-	1	Covered	T2,T3,T15
StManualRun_sparse	-	-	-	-	-	0	Covered	T2,T3,T15
StFlush_sparse	-	-	-	-	-	-	Covered	T1,T2,T3
StTerminalError_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	332	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Covered	T1,T2,T3
MuxRelease	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	351	case (st)
-2-:	353	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	364	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	375	if ((start_i || process_i))
-5-:	385	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	396	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T26,T27,T28
StIdle_sparse	0	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	Covered	T26,T27,T28
StAbsorb_sparse	-	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	1	-	Covered	T26,T27,T28
StManualRun_sparse	-	-	-	0	-	Covered	T2,T3,T15
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T4,T5,T6

---

Assert Coverage for Module : sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	2147483647	10832257	0	0
FsmKnown_A	2147483647	2147483647	0	0
KeccakIdleWhenNoRunHs_A	2147483647	77190683	0	0
MuxSelKnown_A	2147483647	2147483647	0	0
SwRunInSqueezing_a	2147483647	152566	0	0
gen_chk_digest_unmasked.StateZeroInvalid_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10832257	0	0
T4	2949	0	0	0
T26	391383	40596	0	0
T27	0	21439	0	0
T28	0	211847	0	0
T45	0	94515	0	0
T48	306508	0	0	0
T49	277415	0	0	0
T53	0	97507	0	0
T62	98871	0	0	0
T89	0	273251	0	0
T90	0	63196	0	0
T91	0	110453	0	0
T92	0	201655	0	0
T93	0	13777	0	0
T94	490454	0	0	0
T95	86354	0	0	0
T96	240304	0	0	0
T97	98068	0	0	0
T98	614398	0	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	507265	0	0
T2	309893	309801	0	0
T3	136243	136237	0	0
T13	170878	170878	0	0
T14	662368	662359	0	0
T15	491060	490981	0	0
T16	607739	607732	0	0
T17	368693	368638	0	0
T18	138477	138408	0	0
T19	930624	930618	0	0

KeccakIdleWhenNoRunHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	77190683	0	0
T1	507271	315528	0	0
T2	309893	8544	0	0
T3	136243	30480	0	0
T13	170878	315528	0	0
T14	662368	133008	0	0
T15	491060	110208	0	0
T16	607739	132624	0	0
T17	368693	33624	0	0
T18	138477	10416	0	0
T19	930624	142656	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	507265	0	0
T2	309893	309801	0	0
T3	136243	136237	0	0
T13	170878	170878	0	0
T14	662368	662359	0	0
T15	491060	490981	0	0
T16	607739	607732	0	0
T17	368693	368638	0	0
T18	138477	138408	0	0
T19	930624	930618	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	152566	0	0
T2	309893	132	0	0
T3	136243	502	0	0
T13	170878	0	0	0
T14	662368	0	0	0
T15	491060	370	0	0
T16	607739	0	0	0
T17	368693	534	0	0
T18	138477	33	0	0
T19	930624	462	0	0
T23	0	316	0	0
T24	0	233	0	0
T37	0	571	0	0
T88	170625	523	0	0

gen_chk_digest_unmasked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	463341	0	0
T2	309893	204864	0	0
T3	136243	840622	0	0
T13	170878	158817	0	0
T14	662368	642978	0	0
T15	491060	400424	0	0
T16	607739	589198	0	0
T17	368693	237250	0	0
T18	138477	110248	0	0
T19	930624	875111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	507265	0	0
T2	309893	309801	0	0
T3	136243	136237	0	0
T13	170878	170878	0	0
T14	662368	662359	0	0
T15	491060	490981	0	0
T16	607739	607732	0	0
T17	368693	368638	0	0
T18	138477	138408	0	0
T19	930624	930618	0	0

Line Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
TOTAL		82	80	97.56
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	5	5	100.00
ALWAYS	198	3	3	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	207	6	6	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	227	3	3	100.00
ALWAYS	237	38	38	100.00
ALWAYS	332	3	3	100.00
ALWAYS	349	12	10	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
144	1	1
148	1	1
172	1	1
173	1	1
178	1	1
179	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
198	2	2
199	1	1
203	1	1
207	2	2
208	2	2
209	1	1
210	1	1
			MISSING_ELSE
214	1	1
217	1	1
218	1	1
220	1	1
227	3	3
237	1	1
240	1	1
241	1	1
242	1	1
243	1	1
245	1	1
247	1	1
248	1	1
250	1	1
252	1	1
254	1	1
255	1	1
257	1	1
259	1	1
264	1	1
265	1	1
267	1	1
268	1	1
269	1	1
271	1	1
276	1	1
277	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
288	1	1
290	1	1
295	1	1
296	1	1
298	1	1
303	1	1
308	1	1
309	1	1
321	1	1
322	1	1
			MISSING_ELSE
332	1	1
333	1	1
334	1	1
349	1	1
351	1	1
353	1	1
355	1	1
			MISSING_ELSE
364	1	1
366	1	1
			MISSING_ELSE
375	1	1
376	0	1
			MISSING_ELSE
385	1	1
387	1	1
			MISSING_ELSE
396	1	1
398	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T10,T11,T12

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	255	Covered	T1,T2,T3
StFlush_sparse	286	Covered	T1,T2,T3
StIdle_sparse	259	Covered	T1,T2,T3
StManualRun_sparse	282	Covered	T2,T3,T15
StSqueeze_sparse	269	Covered	T1,T2,T3
StTerminalError_sparse	308	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorb_sparse->StSqueeze_sparse	269	Covered	T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse	322	Covered	T4,T5,T6
StFlush_sparse->StIdle_sparse	303	Covered	T1,T2,T3
StFlush_sparse->StTerminalError_sparse	322	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse	255	Covered	T1,T2,T3
StIdle_sparse->StTerminalError_sparse	322	Covered	T10,T11,T12
StManualRun_sparse->StSqueeze_sparse	296	Covered	T2,T3,T15
StManualRun_sparse->StTerminalError_sparse	322	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse	286	Covered	T1,T2,T3
StSqueeze_sparse->StManualRun_sparse	282	Covered	T2,T3,T15
StSqueeze_sparse->StTerminalError_sparse	322	Covered	T56

---

Branch Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
Branches		45	42	93.33
TERNARY	173	3	3	100.00
TERNARY	179	3	3	100.00
IF	184	2	2	100.00
IF	198	2	2	100.00
IF	207	4	4	100.00
IF	227	2	2	100.00
CASE	252	13	13	100.00
IF	321	2	2	100.00
CASE	332	3	2	66.67
CASE	351	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	173	((sha3pad_keccak_run || sw_keccak_run)) ? 
-2-:	173	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	179	(keccak_run) ? 
-2-:	179	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	198	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	207	if ((!rst_ni))
-2-:	208	if (process_i)
-3-:	209	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	case (st)
-2-:	254	if (start_i)
-3-:	264	if ((process_i && (!processing)))
-4-:	268	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	281	if (run_i)
-6-:	285	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	295	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle_sparse	0	-	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	1	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	1	-	-	Covered	T2,T3,T15
StSqueeze_sparse	-	-	-	0	1	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	0	0	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	-	-	1	Covered	T2,T3,T15
StManualRun_sparse	-	-	-	-	-	0	Covered	T2,T3,T15
StFlush_sparse	-	-	-	-	-	-	Covered	T1,T2,T3
StTerminalError_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	332	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Covered	T1,T2,T3
MuxRelease	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	351	case (st)
-2-:	353	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	364	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	375	if ((start_i || process_i))
-5-:	385	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	396	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T26,T27,T28
StIdle_sparse	0	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	Covered	T26,T27,T28
StAbsorb_sparse	-	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	1	-	Covered	T26,T27,T28
StManualRun_sparse	-	-	-	0	-	Covered	T2,T3,T15
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	2147483647	10832257	0	0
FsmKnown_A	2147483647	2147483647	0	0
KeccakIdleWhenNoRunHs_A	2147483647	77190683	0	0
MuxSelKnown_A	2147483647	2147483647	0	0
SwRunInSqueezing_a	2147483647	152566	0	0
gen_chk_digest_unmasked.StateZeroInvalid_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10832257	0	0
T4	2949	0	0	0
T26	391383	40596	0	0
T27	0	21439	0	0
T28	0	211847	0	0
T45	0	94515	0	0
T48	306508	0	0	0
T49	277415	0	0	0
T53	0	97507	0	0
T62	98871	0	0	0
T89	0	273251	0	0
T90	0	63196	0	0
T91	0	110453	0	0
T92	0	201655	0	0
T93	0	13777	0	0
T94	490454	0	0	0
T95	86354	0	0	0
T96	240304	0	0	0
T97	98068	0	0	0
T98	614398	0	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	507265	0	0
T2	309893	309801	0	0
T3	136243	136237	0	0
T13	170878	170878	0	0
T14	662368	662359	0	0
T15	491060	490981	0	0
T16	607739	607732	0	0
T17	368693	368638	0	0
T18	138477	138408	0	0
T19	930624	930618	0	0

KeccakIdleWhenNoRunHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	77190683	0	0
T1	507271	315528	0	0
T2	309893	8544	0	0
T3	136243	30480	0	0
T13	170878	315528	0	0
T14	662368	133008	0	0
T15	491060	110208	0	0
T16	607739	132624	0	0
T17	368693	33624	0	0
T18	138477	10416	0	0
T19	930624	142656	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	507265	0	0
T2	309893	309801	0	0
T3	136243	136237	0	0
T13	170878	170878	0	0
T14	662368	662359	0	0
T15	491060	490981	0	0
T16	607739	607732	0	0
T17	368693	368638	0	0
T18	138477	138408	0	0
T19	930624	930618	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	152566	0	0
T2	309893	132	0	0
T3	136243	502	0	0
T13	170878	0	0	0
T14	662368	0	0	0
T15	491060	370	0	0
T16	607739	0	0	0
T17	368693	534	0	0
T18	138477	33	0	0
T19	930624	462	0	0
T23	0	316	0	0
T24	0	233	0	0
T37	0	571	0	0
T88	170625	523	0	0

gen_chk_digest_unmasked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	463341	0	0
T2	309893	204864	0	0
T3	136243	840622	0	0
T13	170878	158817	0	0
T14	662368	642978	0	0
T15	491060	400424	0	0
T16	607739	589198	0	0
T17	368693	237250	0	0
T18	138477	110248	0	0
T19	930624	875111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	507271	507265	0	0
T2	309893	309801	0	0
T3	136243	136237	0	0
T13	170878	170878	0	0
T14	662368	662359	0	0
T15	491060	490981	0	0
T16	607739	607732	0	0
T17	368693	368638	0	0
T18	138477	138408	0	0
T19	930624	930618	0	0