Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	717090	0	0
entropy_period_rd_A	2147483647	1774	0	0
intr_enable_rd_A	2147483647	2202	0	0
prefix_0_rd_A	2147483647	1589	0	0
prefix_10_rd_A	2147483647	1524	0	0
prefix_1_rd_A	2147483647	1629	0	0
prefix_2_rd_A	2147483647	1544	0	0
prefix_3_rd_A	2147483647	1547	0	0
prefix_4_rd_A	2147483647	1510	0	0
prefix_5_rd_A	2147483647	1487	0	0
prefix_6_rd_A	2147483647	1560	0	0
prefix_7_rd_A	2147483647	1455	0	0
prefix_8_rd_A	2147483647	1716	0	0
prefix_9_rd_A	2147483647	1517	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	717090	0	0
T53	245659	37903	0	0
T54	0	81424	0	0
T55	0	22609	0	0
T81	0	61234	0	0
T89	169576	0	0	0
T128	0	19956	0	0
T129	0	36220	0	0
T130	0	63069	0	0
T131	0	18946	0	0
T132	0	92961	0	0
T133	0	95074	0	0
T134	21138	0	0	0
T135	140528	0	0	0
T136	172229	0	0	0
T137	460317	0	0	0
T138	176392	0	0	0
T139	7165	0	0	0
T140	137280	0	0	0
T141	179129	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T101	8209	21	0	0
T103	3176	16	0	0
T118	6752	29	0	0
T121	12093	54	0	0
T122	12348	50	0	0
T150	10875	56	0	0
T151	11726	39	0	0
T152	62188	68	0	0
T153	23012	139	0	0
T154	11747	92	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2202	0	0
T101	8209	15	0	0
T103	3176	11	0	0
T118	6752	31	0	0
T121	12093	66	0	0
T122	12348	68	0	0
T150	10875	16	0	0
T151	11726	25	0	0
T155	1346	12	0	0
T156	1205	22	0	0
T157	1359	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T101	8209	18	0	0
T103	3176	16	0	0
T118	6752	43	0	0
T121	12093	44	0	0
T122	12348	31	0	0
T150	10875	37	0	0
T151	11726	64	0	0
T152	62188	120	0	0
T153	23012	87	0	0
T154	11747	57	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1524	0	0
T101	8209	22	0	0
T103	3176	11	0	0
T118	6752	21	0	0
T121	12093	49	0	0
T122	12348	48	0	0
T150	10875	44	0	0
T151	11726	74	0	0
T152	62188	126	0	0
T153	23012	86	0	0
T154	11747	58	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1629	0	0
T101	8209	32	0	0
T103	3176	15	0	0
T118	6752	27	0	0
T121	12093	53	0	0
T122	12348	43	0	0
T150	10875	54	0	0
T151	11726	46	0	0
T152	62188	153	0	0
T153	23012	98	0	0
T154	11747	48	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1544	0	0
T101	8209	17	0	0
T103	3176	13	0	0
T118	6752	16	0	0
T121	12093	40	0	0
T122	12348	35	0	0
T150	10875	30	0	0
T151	11726	16	0	0
T152	62188	152	0	0
T153	23012	67	0	0
T154	11747	44	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T101	8209	21	0	0
T103	3176	11	0	0
T118	6752	30	0	0
T121	12093	45	0	0
T122	12348	55	0	0
T150	10875	51	0	0
T151	11726	40	0	0
T152	62188	128	0	0
T153	23012	67	0	0
T154	11747	64	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1510	0	0
T101	8209	19	0	0
T103	3176	6	0	0
T118	6752	33	0	0
T121	12093	46	0	0
T122	12348	55	0	0
T150	10875	52	0	0
T151	11726	45	0	0
T152	62188	136	0	0
T153	23012	78	0	0
T154	11747	41	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1487	0	0
T101	8209	26	0	0
T103	3176	10	0	0
T118	6752	28	0	0
T121	12093	37	0	0
T122	12348	33	0	0
T150	10875	28	0	0
T151	11726	35	0	0
T152	62188	154	0	0
T153	23012	50	0	0
T158	14953	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1560	0	0
T101	8209	21	0	0
T103	3176	7	0	0
T118	6752	21	0	0
T121	12093	28	0	0
T122	12348	28	0	0
T150	10875	47	0	0
T151	11726	62	0	0
T152	62188	133	0	0
T153	23012	92	0	0
T154	11747	61	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1455	0	0
T101	8209	12	0	0
T103	3176	15	0	0
T118	6752	31	0	0
T121	12093	47	0	0
T122	12348	43	0	0
T150	10875	54	0	0
T151	11726	27	0	0
T152	62188	120	0	0
T153	23012	72	0	0
T154	11747	62	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1716	0	0
T101	8209	15	0	0
T103	3176	15	0	0
T118	6752	20	0	0
T121	12093	32	0	0
T122	12348	31	0	0
T150	10875	72	0	0
T151	11726	39	0	0
T152	62188	155	0	0
T153	23012	89	0	0
T159	13480	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1517	0	0
T101	8209	27	0	0
T103	3176	9	0	0
T118	6752	40	0	0
T121	12093	50	0	0
T122	12348	56	0	0
T150	10875	58	0	0
T151	11726	28	0	0
T152	62188	107	0	0
T153	23012	72	0	0
T159	13480	1	0	0