Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258667681

1

T1

9487

T2

119342

T3

18645

full_word

202145288

1

T1

20698

T2

83583

T3

30170

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	460812659	1			T1	30185		T2	202925		T3	48815
auto[TlIntgErrCmd]	122	1			T104	3		T105	9		T106	4
auto[TlIntgErrData]	109	1			T104	4		T105	7		T106	2
auto[TlIntgErrBoth]	79	1			T104	3		T105	4		T106	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242359003

1

T1

21755

T2

106302

T3

33976

auto[1]

218453966

1

T1

8430

T2

96623

T3

14839

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154083963	1			T1	5801		T2	71815		T3	11786
auto[TlIntgErrNone]	partial	auto[1]	104583435	1			T1	3686		T2	47527		T3	6859
auto[TlIntgErrNone]	full_word	auto[0]	88274885	1			T1	15954		T2	34487		T3	22190
auto[TlIntgErrNone]	full_word	auto[1]	113870376	1			T1	4744		T2	49096		T3	7980
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T104	1		T105	7		T106	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T104	2		T105	2		T106	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T160	1		T165	1		T164	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T165	2		T166	1		T167	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T104	2		T105	4		T160	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T104	2		T105	3		T106	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T162	1		T168	2		T169	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T163	1		T170	1		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T104	2		T105	2		T106	3
auto[TlIntgErrBoth]	partial	auto[1]	27	1			T104	1		T105	2		T106	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T169	1		T172	1		T173	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T174	1		T175	1		T173	1