Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	600174	0	0
entropy_period_rd_A	2147483647	1653	0	0
intr_enable_rd_A	2147483647	2506	0	0
prefix_0_rd_A	2147483647	1654	0	0
prefix_10_rd_A	2147483647	1591	0	0
prefix_1_rd_A	2147483647	1702	0	0
prefix_2_rd_A	2147483647	1579	0	0
prefix_3_rd_A	2147483647	1704	0	0
prefix_4_rd_A	2147483647	1791	0	0
prefix_5_rd_A	2147483647	1622	0	0
prefix_6_rd_A	2147483647	1663	0	0
prefix_7_rd_A	2147483647	1714	0	0
prefix_8_rd_A	2147483647	1720	0	0
prefix_9_rd_A	2147483647	1640	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	600174	0	0
T44	213806	17349	0	0
T45	0	92615	0	0
T46	0	52069	0	0
T77	477873	0	0	0
T78	603241	0	0	0
T110	0	23115	0	0
T111	0	81342	0	0
T112	0	28313	0	0
T113	0	100204	0	0
T114	0	48418	0	0
T115	0	51609	0	0
T116	0	19651	0	0
T117	669543	0	0	0
T118	6124	0	0	0
T119	361623	0	0	0
T120	201592	0	0	0
T121	431381	0	0	0
T122	89408	0	0	0
T123	399175	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653	0	0
T98	4590	6	0	0
T105	24032	98	0	0
T130	7259	26	0	0
T131	7102	31	0	0
T132	5224	28	0	0
T133	3067	2	0	0
T134	5020	5	0	0
T135	5352	13	0	0
T136	2378	1	0	0
T137	7686	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2506	0	0
T105	24032	196	0	0
T109	1415	6	0	0
T130	7259	12	0	0
T131	7102	25	0	0
T132	5224	2	0	0
T133	3067	15	0	0
T134	5020	16	0	0
T138	916	11	0	0
T139	1552	8	0	0
T140	1768	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1654	0	0
T98	4590	5	0	0
T105	24032	59	0	0
T130	7259	16	0	0
T131	7102	13	0	0
T132	5224	9	0	0
T133	3067	11	0	0
T134	5020	7	0	0
T135	5352	9	0	0
T136	2378	7	0	0
T137	7686	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T98	4590	4	0	0
T105	24032	72	0	0
T130	7259	12	0	0
T131	7102	8	0	0
T133	3067	8	0	0
T134	5020	6	0	0
T135	5352	7	0	0
T136	2378	5	0	0
T137	7686	14	0	0
T141	1527	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1702	0	0
T98	4590	7	0	0
T105	24032	91	0	0
T130	7259	14	0	0
T131	7102	24	0	0
T132	5224	6	0	0
T133	3067	10	0	0
T134	5020	4	0	0
T135	5352	14	0	0
T137	7686	21	0	0
T142	2329	3	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T98	4590	4	0	0
T105	24032	77	0	0
T130	7259	13	0	0
T131	7102	35	0	0
T132	5224	17	0	0
T133	3067	15	0	0
T134	5020	6	0	0
T135	5352	16	0	0
T136	2378	1	0	0
T137	7686	13	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1704	0	0
T105	24032	70	0	0
T130	7259	25	0	0
T131	7102	1	0	0
T132	5224	16	0	0
T133	3067	13	0	0
T134	5020	7	0	0
T135	5352	12	0	0
T136	2378	5	0	0
T137	7686	11	0	0
T141	1527	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1791	0	0
T98	4590	6	0	0
T105	24032	73	0	0
T130	7259	18	0	0
T131	7102	33	0	0
T132	5224	12	0	0
T133	3067	13	0	0
T134	5020	9	0	0
T135	5352	10	0	0
T136	2378	2	0	0
T137	7686	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1622	0	0
T98	4590	5	0	0
T105	24032	81	0	0
T130	7259	30	0	0
T131	7102	10	0	0
T132	5224	5	0	0
T133	3067	3	0	0
T134	5020	11	0	0
T135	5352	9	0	0
T136	2378	6	0	0
T137	7686	14	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T98	4590	11	0	0
T105	24032	77	0	0
T130	7259	15	0	0
T131	7102	38	0	0
T132	5224	28	0	0
T133	3067	12	0	0
T134	5020	2	0	0
T135	5352	8	0	0
T136	2378	5	0	0
T137	7686	12	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1714	0	0
T98	4590	12	0	0
T105	24032	84	0	0
T130	7259	5	0	0
T131	7102	18	0	0
T132	5224	9	0	0
T133	3067	9	0	0
T134	5020	4	0	0
T135	5352	3	0	0
T136	2378	6	0	0
T137	7686	16	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1720	0	0
T105	24032	81	0	0
T130	7259	10	0	0
T131	7102	45	0	0
T133	3067	8	0	0
T134	5020	11	0	0
T135	5352	9	0	0
T136	2378	4	0	0
T137	7686	26	0	0
T142	2329	4	0	0
T143	3252	13	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1640	0	0
T98	4590	2	0	0
T105	24032	58	0	0
T130	7259	16	0	0
T131	7102	13	0	0
T132	5224	18	0	0
T133	3067	4	0	0
T134	5020	10	0	0
T135	5352	10	0	0
T136	2378	7	0	0
T137	7686	16	0	0