Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255040320

1

T1

29382

T2

621

T3

554030

full_word

201374933

1

T1

41599

T2

1414

T3

359200

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456414973	1			T1	70981		T2	2035		T3	913230
auto[TlIntgErrCmd]	83	1			T123	5		T124	5		T125	3
auto[TlIntgErrData]	115	1			T123	8		T124	3		T125	4
auto[TlIntgErrBoth]	82	1			T123	7		T124	2		T125	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240184200

1

T1

47493

T2

1063

T3

466047

auto[1]

216231053

1

T1

23488

T2

972

T3

447183

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152469271	1			T1	18246		T2	379		T3	332480
auto[TlIntgErrNone]	partial	auto[1]	102570804	1			T1	11136		T2	242		T3	221550
auto[TlIntgErrNone]	full_word	auto[0]	87714809	1			T1	29247		T2	684		T3	133567
auto[TlIntgErrNone]	full_word	auto[1]	113660089	1			T1	12352		T2	730		T3	225633
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T123	2		T124	3		T125	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T123	3		T124	1		T125	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T183	1		T188	2		T185	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T124	1		T186	1		T189	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T123	3		T124	2		T125	1
auto[TlIntgErrData]	partial	auto[1]	56	1			T123	3		T124	1		T125	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T123	1		T159	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	13	1			T123	1		T125	1		T190	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T123	1		T124	2		T125	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T123	6		T125	2		T182	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T191	1		T192	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T129	1		T193	1		T189	1