Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	231766	0	0
entropy_period_rd_A	2147483647	2681	0	0
intr_enable_rd_A	2147483647	3243	0	0
prefix_0_rd_A	2147483647	2407	0	0
prefix_10_rd_A	2147483647	2417	0	0
prefix_1_rd_A	2147483647	2231	0	0
prefix_2_rd_A	2147483647	2322	0	0
prefix_3_rd_A	2147483647	2506	0	0
prefix_4_rd_A	2147483647	2213	0	0
prefix_5_rd_A	2147483647	2477	0	0
prefix_6_rd_A	2147483647	2341	0	0
prefix_7_rd_A	2147483647	2287	0	0
prefix_8_rd_A	2147483647	2209	0	0
prefix_9_rd_A	2147483647	2419	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	231766	0	0
T57	238727	16290	0	0
T58	0	70052	0	0
T59	0	24339	0	0
T123	0	3	0	0
T125	0	1	0	0
T130	0	83321	0	0
T131	0	34603	0	0
T132	0	12	0	0
T133	0	144	0	0
T134	0	20	0	0
T135	58749	0	0	0
T136	26360	0	0	0
T137	836016	0	0	0
T138	416612	0	0	0
T139	324917	0	0	0
T140	4428	0	0	0
T141	613597	0	0	0
T142	485380	0	0	0
T143	170849	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T58	809900	221	0	0
T59	0	47	0	0
T110	0	20	0	0
T125	0	55	0	0
T144	0	9	0	0
T156	0	108	0	0
T157	0	11	0	0
T158	0	23	0	0
T159	0	136	0	0
T160	0	24	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3243	0	0
T58	809900	135	0	0
T59	0	44	0	0
T110	0	16	0	0
T125	0	61	0	0
T144	0	13	0	0
T156	0	212	0	0
T157	0	1	0	0
T158	0	46	0	0
T159	0	153	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0
T170	0	24	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2407	0	0
T58	809900	171	0	0
T59	0	34	0	0
T110	0	17	0	0
T125	0	41	0	0
T144	0	8	0	0
T156	0	240	0	0
T157	0	10	0	0
T158	0	5	0	0
T159	0	51	0	0
T160	0	25	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2417	0	0
T58	809900	129	0	0
T59	0	31	0	0
T110	0	14	0	0
T125	0	38	0	0
T144	0	3	0	0
T156	0	272	0	0
T157	0	5	0	0
T158	0	19	0	0
T159	0	89	0	0
T160	0	20	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2231	0	0
T58	809900	189	0	0
T59	0	38	0	0
T110	0	3	0	0
T125	0	36	0	0
T144	0	7	0	0
T156	0	214	0	0
T157	0	10	0	0
T158	0	21	0	0
T159	0	73	0	0
T160	0	14	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2322	0	0
T58	809900	155	0	0
T59	0	25	0	0
T110	0	9	0	0
T125	0	37	0	0
T144	0	4	0	0
T156	0	241	0	0
T157	0	14	0	0
T158	0	19	0	0
T159	0	70	0	0
T160	0	21	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2506	0	0
T58	809900	195	0	0
T59	0	71	0	0
T110	0	4	0	0
T125	0	39	0	0
T144	0	8	0	0
T156	0	200	0	0
T157	0	5	0	0
T158	0	48	0	0
T159	0	100	0	0
T160	0	6	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T58	809900	153	0	0
T59	0	47	0	0
T110	0	11	0	0
T125	0	36	0	0
T144	0	1	0	0
T156	0	232	0	0
T157	0	3	0	0
T158	0	27	0	0
T159	0	75	0	0
T160	0	3	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2477	0	0
T58	809900	214	0	0
T59	0	19	0	0
T110	0	12	0	0
T125	0	34	0	0
T144	0	8	0	0
T156	0	249	0	0
T157	0	6	0	0
T158	0	50	0	0
T159	0	120	0	0
T160	0	10	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T58	809900	156	0	0
T59	0	33	0	0
T110	0	16	0	0
T125	0	52	0	0
T144	0	5	0	0
T156	0	196	0	0
T157	0	7	0	0
T158	0	55	0	0
T159	0	108	0	0
T160	0	10	0	0
T161	179851	0	0	0
T162	173701	0	0	0
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T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T58	809900	186	0	0
T59	0	22	0	0
T110	0	18	0	0
T125	0	41	0	0
T144	0	11	0	0
T156	0	213	0	0
T157	0	7	0	0
T158	0	12	0	0
T159	0	74	0	0
T160	0	16	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2209	0	0
T58	809900	143	0	0
T59	0	27	0	0
T110	0	8	0	0
T125	0	26	0	0
T144	0	9	0	0
T156	0	212	0	0
T157	0	8	0	0
T158	0	28	0	0
T159	0	71	0	0
T160	0	15	0	0
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T162	173701	0	0	0
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T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2419	0	0
T58	809900	237	0	0
T59	0	59	0	0
T110	0	3	0	0
T125	0	47	0	0
T129	0	85	0	0
T144	0	9	0	0
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T158	0	3	0	0
T159	0	73	0	0
T160	0	27	0	0
T161	179851	0	0	0
T162	173701	0	0	0
T163	644265	0	0	0
T164	455729	0	0	0
T165	225877	0	0	0
T166	436185	0	0	0
T167	2979	0	0	0
T168	145476	0	0	0
T169	870323	0	0	0