Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260572755

1

T1

741

T2

409

T3

650

full_word

202576518

1

T1

1386

T2

11353

T3

1421

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	463148953	1			T1	2127		T2	11762		T3	2071
auto[TlIntgErrCmd]	112	1			T114	7		T115	1		T116	3
auto[TlIntgErrData]	96	1			T114	7		T115	4		T116	2
auto[TlIntgErrBoth]	112	1			T114	6		T115	5		T116	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243439978

1

T1

1107

T2

9831

T3

1079

auto[1]

219709295

1

T1

1020

T2

1931

T3

992

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154972234	1			T1	425		T2	196		T3	382
auto[TlIntgErrNone]	partial	auto[1]	105600228	1			T1	316		T2	213		T3	268
auto[TlIntgErrNone]	full_word	auto[0]	88467603	1			T1	682		T2	9635		T3	697
auto[TlIntgErrNone]	full_word	auto[1]	114108888	1			T1	704		T2	1718		T3	724
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T114	3		T115	1		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T114	3		T116	2		T177	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T114	1		T184	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T178	3		T185	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T114	2		T115	2		T116	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T114	5		T115	2		T116	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T187	1		T181	2		T188	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T177	1		T181	1		T184	3
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T114	2		T115	2		T116	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T114	4		T115	3		T116	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T183	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T178	1		T189	1		T179	1