Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	694826	0	0
entropy_period_rd_A	2147483647	2508	0	0
intr_enable_rd_A	2147483647	3257	0	0
prefix_0_rd_A	2147483647	2402	0	0
prefix_10_rd_A	2147483647	2284	0	0
prefix_1_rd_A	2147483647	2432	0	0
prefix_2_rd_A	2147483647	2539	0	0
prefix_3_rd_A	2147483647	2400	0	0
prefix_4_rd_A	2147483647	2317	0	0
prefix_5_rd_A	2147483647	2238	0	0
prefix_6_rd_A	2147483647	2397	0	0
prefix_7_rd_A	2147483647	2404	0	0
prefix_8_rd_A	2147483647	2407	0	0
prefix_9_rd_A	2147483647	2225	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	694826	0	0
T25	95564	0	0	0
T44	0	24968	0	0
T50	448467	69906	0	0
T51	0	72249	0	0
T120	0	11701	0	0
T121	0	50705	0	0
T122	0	26090	0	0
T123	0	17899	0	0
T124	0	53251	0	0
T125	0	21852	0	0
T126	0	114015	0	0
T127	213098	0	0	0
T128	6306	0	0	0
T129	170326	0	0	0
T130	23917	0	0	0
T131	319715	0	0	0
T132	25217	0	0	0
T133	253330	0	0	0
T134	504388	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2508	0	0
T38	100349	0	0	0
T51	804250	180	0	0
T96	0	48	0	0
T97	0	19	0	0
T98	0	45	0	0
T99	0	13	0	0
T104	0	15	0	0
T143	0	10	0	0
T144	0	85	0	0
T145	0	14	0	0
T146	0	11	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3257	0	0
T38	100349	0	0	0
T51	804250	183	0	0
T96	0	76	0	0
T97	0	22	0	0
T98	0	54	0	0
T99	0	18	0	0
T104	0	16	0	0
T117	0	39	0	0
T118	0	4	0	0
T143	0	19	0	0
T144	0	14	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2402	0	0
T38	100349	0	0	0
T51	804250	172	0	0
T96	0	32	0	0
T97	0	13	0	0
T98	0	53	0	0
T99	0	19	0	0
T104	0	29	0	0
T143	0	11	0	0
T144	0	33	0	0
T146	0	12	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0
T155	0	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2284	0	0
T38	100349	0	0	0
T51	804250	123	0	0
T96	0	18	0	0
T97	0	6	0	0
T98	0	32	0	0
T99	0	11	0	0
T104	0	11	0	0
T143	0	6	0	0
T144	0	30	0	0
T145	0	3	0	0
T146	0	7	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2432	0	0
T38	100349	0	0	0
T51	804250	165	0	0
T96	0	26	0	0
T97	0	12	0	0
T98	0	24	0	0
T99	0	20	0	0
T104	0	8	0	0
T143	0	7	0	0
T144	0	51	0	0
T145	0	31	0	0
T146	0	11	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2539	0	0
T38	100349	0	0	0
T51	804250	166	0	0
T96	0	44	0	0
T97	0	15	0	0
T98	0	34	0	0
T99	0	22	0	0
T104	0	9	0	0
T143	0	7	0	0
T144	0	46	0	0
T145	0	2	0	0
T146	0	4	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2400	0	0
T38	100349	0	0	0
T51	804250	195	0	0
T96	0	20	0	0
T97	0	18	0	0
T98	0	49	0	0
T99	0	27	0	0
T104	0	19	0	0
T143	0	12	0	0
T144	0	32	0	0
T145	0	6	0	0
T146	0	15	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2317	0	0
T38	100349	0	0	0
T51	804250	121	0	0
T96	0	19	0	0
T97	0	6	0	0
T98	0	43	0	0
T99	0	18	0	0
T104	0	2	0	0
T143	0	14	0	0
T144	0	21	0	0
T145	0	10	0	0
T146	0	3	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2238	0	0
T38	100349	0	0	0
T51	804250	141	0	0
T96	0	23	0	0
T97	0	22	0	0
T98	0	38	0	0
T99	0	26	0	0
T104	0	21	0	0
T143	0	11	0	0
T144	0	34	0	0
T145	0	4	0	0
T146	0	1	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2397	0	0
T38	100349	0	0	0
T51	804250	228	0	0
T96	0	25	0	0
T97	0	19	0	0
T98	0	21	0	0
T99	0	22	0	0
T104	0	11	0	0
T143	0	11	0	0
T144	0	42	0	0
T145	0	12	0	0
T146	0	8	0	0
T147	1060	0	0	0
T148	322821	0	0	0
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T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T38	100349	0	0	0
T51	804250	206	0	0
T96	0	16	0	0
T97	0	11	0	0
T98	0	42	0	0
T99	0	20	0	0
T104	0	6	0	0
T143	0	3	0	0
T144	0	40	0	0
T145	0	3	0	0
T146	0	6	0	0
T147	1060	0	0	0
T148	322821	0	0	0
T149	280848	0	0	0
T150	105020	0	0	0
T151	19943	0	0	0
T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2407	0	0
T38	100349	0	0	0
T51	804250	180	0	0
T96	0	41	0	0
T97	0	16	0	0
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T99	0	25	0	0
T104	0	1	0	0
T143	0	5	0	0
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T152	16721	0	0	0
T153	864	0	0	0
T154	24049	0	0	0
T156	0	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T38	100349	0	0	0
T51	804250	112	0	0
T96	0	7	0	0
T97	0	13	0	0
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T147	1060	0	0	0
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T151	19943	0	0	0
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T155	0	7	0	0