Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

252876119

1

T1

518757

T2

547167

T3

22791

full_word

197401864

1

T1

339734

T2

359552

T3

42326

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450277663	1			T1	858491		T2	906719		T3	65117
auto[TlIntgErrCmd]	107	1			T122	8		T123	7		T124	1
auto[TlIntgErrData]	100	1			T122	8		T123	5		T124	5
auto[TlIntgErrBoth]	113	1			T122	4		T123	8		T124	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236896902

1

T1

438473

T2

462783

T3

46079

auto[1]

213381081

1

T1

420018

T2

443936

T3

19038

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	150710162	1			T1	312453		T2	330186		T3	15000
auto[TlIntgErrNone]	partial	auto[1]	102165671	1			T1	206304		T2	216981		T3	7791
auto[TlIntgErrNone]	full_word	auto[0]	86186599	1			T1	126020		T2	132597		T3	31079
auto[TlIntgErrNone]	full_word	auto[1]	111215231	1			T1	213714		T2	226955		T3	11247
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T122	3		T123	2		T124	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T122	5		T123	4		T179	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T182	1		T184	2		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T123	1		T179	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T122	1		T123	1		T124	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T122	4		T123	3		T124	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T122	1		T179	1		T186	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T122	2		T123	1		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T122	2		T123	2		T124	4
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T122	2		T123	5		T179	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T187	1		T185	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T123	1		T180	1		T183	1