Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	473542	0	0
entropy_period_rd_A	2147483647	1806	0	0
intr_enable_rd_A	2147483647	2458	0	0
prefix_0_rd_A	2147483647	1497	0	0
prefix_10_rd_A	2147483647	1592	0	0
prefix_1_rd_A	2147483647	1678	0	0
prefix_2_rd_A	2147483647	1574	0	0
prefix_3_rd_A	2147483647	1648	0	0
prefix_4_rd_A	2147483647	1648	0	0
prefix_5_rd_A	2147483647	1596	0	0
prefix_6_rd_A	2147483647	1635	0	0
prefix_7_rd_A	2147483647	1537	0	0
prefix_8_rd_A	2147483647	1582	0	0
prefix_9_rd_A	2147483647	1723	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	473542	0	0
T32	880679	0	0	0
T48	634903	60918	0	0
T49	0	15128	0	0
T50	0	70348	0	0
T61	97315	0	0	0
T128	0	57413	0	0
T129	0	142769	0	0
T130	0	22984	0	0
T131	0	14041	0	0
T132	0	14849	0	0
T133	0	54038	0	0
T134	0	18417	0	0
T135	200194	0	0	0
T136	749442	0	0	0
T137	42585	0	0	0
T138	24329	0	0	0
T139	189629	0	0	0
T140	50760	0	0	0
T141	548787	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1806	0	0
T49	211874	46	0	0
T109	0	61	0	0
T110	0	4	0	0
T122	0	121	0	0
T132	0	30	0	0
T133	0	67	0	0
T134	0	63	0	0
T149	0	6	0	0
T150	0	28	0	0
T151	0	401	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2458	0	0
T49	211874	46	0	0
T126	0	13	0	0
T132	0	73	0	0
T133	0	85	0	0
T134	0	67	0	0
T149	0	7	0	0
T150	0	50	0	0
T151	0	450	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0
T161	0	29	0	0
T162	0	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1497	0	0
T49	211874	44	0	0
T110	0	4	0	0
T122	0	83	0	0
T132	0	41	0	0
T133	0	33	0	0
T134	0	43	0	0
T149	0	8	0	0
T150	0	25	0	0
T151	0	418	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0
T163	0	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1592	0	0
T49	211874	36	0	0
T109	0	47	0	0
T122	0	66	0	0
T132	0	41	0	0
T133	0	47	0	0
T134	0	37	0	0
T149	0	7	0	0
T150	0	23	0	0
T151	0	451	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0
T164	0	27	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T49	211874	85	0	0
T109	0	39	0	0
T110	0	8	0	0
T122	0	74	0	0
T132	0	45	0	0
T133	0	44	0	0
T134	0	64	0	0
T149	0	6	0	0
T150	0	23	0	0
T151	0	435	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1574	0	0
T49	211874	34	0	0
T109	0	58	0	0
T110	0	3	0	0
T122	0	85	0	0
T132	0	48	0	0
T133	0	81	0	0
T134	0	69	0	0
T150	0	24	0	0
T151	0	442	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0
T164	0	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T49	211874	27	0	0
T109	0	40	0	0
T110	0	3	0	0
T122	0	63	0	0
T132	0	37	0	0
T133	0	63	0	0
T134	0	75	0	0
T149	0	10	0	0
T150	0	31	0	0
T151	0	463	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T49	211874	42	0	0
T109	0	56	0	0
T110	0	13	0	0
T122	0	90	0	0
T132	0	56	0	0
T133	0	46	0	0
T134	0	54	0	0
T149	0	8	0	0
T150	0	17	0	0
T151	0	474	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1596	0	0
T49	211874	43	0	0
T109	0	44	0	0
T110	0	6	0	0
T122	0	76	0	0
T132	0	28	0	0
T133	0	63	0	0
T134	0	50	0	0
T149	0	7	0	0
T150	0	35	0	0
T151	0	475	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T49	211874	42	0	0
T109	0	38	0	0
T110	0	9	0	0
T122	0	116	0	0
T132	0	93	0	0
T133	0	70	0	0
T134	0	71	0	0
T149	0	2	0	0
T150	0	17	0	0
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T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
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T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1537	0	0
T49	211874	47	0	0
T109	0	43	0	0
T110	0	10	0	0
T122	0	78	0	0
T132	0	35	0	0
T133	0	56	0	0
T134	0	46	0	0
T149	0	6	0	0
T150	0	35	0	0
T151	0	388	0	0
T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T49	211874	61	0	0
T109	0	45	0	0
T110	0	5	0	0
T122	0	86	0	0
T132	0	25	0	0
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T152	23628	0	0	0
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T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1723	0	0
T49	211874	68	0	0
T109	0	45	0	0
T110	0	12	0	0
T122	0	107	0	0
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T149	0	1	0	0
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T152	23628	0	0	0
T153	146704	0	0	0
T154	32219	0	0	0
T155	16109	0	0	0
T156	1002	0	0	0
T157	116109	0	0	0
T158	640232	0	0	0
T159	145313	0	0	0
T160	97104	0	0	0