Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 255081545 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 201910036 1 T1 3436 T2 11221 T3 888253



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 240948389 1 T1 3340 T2 11461 T3 109549
values[0x0] 103813632 1 T1 936 T2 2712 T3 444875
values[0x1] 112229560 1 T1 949 T2 2780 T3 479401



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 198817184 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 258174397 1 T1 3804 T2 12398 T3 113464



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1350029 1 T1 6 T2 75 T3 7845
valid_sources[0x01] 1530895 1 T1 37 T2 60 T3 7822
valid_sources[0x02] 1352748 1 T1 25 T2 70 T3 7752
valid_sources[0x03] 1430814 1 T1 12 T2 64 T3 7707
valid_sources[0x04] 1835665 1 T1 21 T2 56 T3 7805
valid_sources[0x05] 1350764 1 T1 38 T2 49 T3 7908
valid_sources[0x06] 2212610 1 T1 28 T2 66 T3 7681
valid_sources[0x07] 1343669 1 T1 13 T2 67 T3 7917
valid_sources[0x08] 1351215 1 T1 11 T2 81 T3 7855
valid_sources[0x09] 1345782 1 T1 3 T2 61 T3 7768
valid_sources[0x0a] 2425117 1 T1 22 T2 59 T3 7812
valid_sources[0x0b] 2229814 1 T1 23 T2 77 T3 7912
valid_sources[0x0c] 2816993 1 T1 32 T2 52 T3 7834
valid_sources[0x0d] 1344963 1 T1 21 T2 68 T3 7937
valid_sources[0x0e] 1356385 1 T1 35 T2 80 T3 7931
valid_sources[0x0f] 1498984 1 T1 15 T2 74 T3 7870
valid_sources[0x10] 1410607 1 T1 21 T2 71 T3 7869
valid_sources[0x11] 1371471 1 T1 39 T2 55 T3 7848
valid_sources[0x12] 1386791 1 T1 17 T2 61 T3 8025
valid_sources[0x13] 1350364 1 T1 14 T2 84 T3 7971
valid_sources[0x14] 1482294 1 T1 13 T2 81 T3 7721
valid_sources[0x15] 2262273 1 T1 19 T2 64 T3 7876
valid_sources[0x16] 1354918 1 T1 23 T2 72 T3 7822
valid_sources[0x17] 1349819 1 T1 15 T2 69 T3 7840
valid_sources[0x18] 1349757 1 T1 25 T2 69 T3 7791
valid_sources[0x19] 1347703 1 T1 19 T2 76 T3 7999
valid_sources[0x1a] 3355524 1 T1 18 T2 69 T3 7847
valid_sources[0x1b] 1347886 1 T1 9 T2 66 T3 7946
valid_sources[0x1c] 1350533 1 T1 5 T2 68 T3 7837
valid_sources[0x1d] 1374842 1 T1 13 T2 52 T3 8065
valid_sources[0x1e] 1351776 1 T1 39 T2 80 T3 8012
valid_sources[0x1f] 2218343 1 T1 40 T2 63 T3 7666
valid_sources[0x20] 1352864 1 T1 38 T2 61 T3 7930
valid_sources[0x21] 1498164 1 T1 7 T2 63 T3 8012
valid_sources[0x22] 2336734 1 T1 22 T2 76 T3 7884
valid_sources[0x23] 2220686 1 T1 18 T2 75 T3 7822
valid_sources[0x24] 1809636 1 T1 20 T2 77 T3 8036
valid_sources[0x25] 1492760 1 T1 12 T2 66 T3 7829
valid_sources[0x26] 1350407 1 T1 17 T2 61 T3 7969
valid_sources[0x27] 1346572 1 T1 31 T2 59 T3 7770
valid_sources[0x28] 3402755 1 T1 11 T2 69 T3 8063
valid_sources[0x29] 1378389 1 T1 13 T2 58 T3 7954
valid_sources[0x2a] 3680955 1 T1 23 T2 54 T3 7940
valid_sources[0x2b] 1607137 1 T1 14 T2 63 T3 7834
valid_sources[0x2c] 1349764 1 T1 5 T2 57 T3 8062
valid_sources[0x2d] 2134147 1 T1 5 T2 50 T3 8050
valid_sources[0x2e] 1347380 1 T1 10 T2 58 T3 7945
valid_sources[0x2f] 2289379 1 T1 11 T2 49 T3 7956
valid_sources[0x30] 1343794 1 T1 21 T2 75 T3 7854
valid_sources[0x31] 1414107 1 T1 19 T2 80 T3 8040
valid_sources[0x32] 1351435 1 T1 39 T2 73 T3 7921
valid_sources[0x33] 1344601 1 T1 11 T2 75 T3 7832
valid_sources[0x34] 1344891 1 T1 17 T2 72 T3 8085
valid_sources[0x35] 1356191 1 T1 30 T2 66 T3 7796
valid_sources[0x36] 1346239 1 T1 4 T2 64 T3 7781
valid_sources[0x37] 1386307 1 T1 20 T2 61 T3 7860
valid_sources[0x38] 3420232 1 T1 15 T2 76 T3 7858
valid_sources[0x39] 3387277 1 T1 13 T2 81 T3 7735
valid_sources[0x3a] 1346078 1 T1 13 T2 72 T3 7970
valid_sources[0x3b] 1349424 1 T1 35 T2 79 T3 7918
valid_sources[0x3c] 1354790 1 T1 19 T2 80 T3 7820
valid_sources[0x3d] 1349565 1 T1 16 T2 68 T3 7840
valid_sources[0x3e] 1439505 1 T1 11 T2 69 T3 7886
valid_sources[0x3f] 1353636 1 T1 21 T2 56 T3 7970
valid_sources[0x40] 1347395 1 T1 4 T2 74 T3 7840
valid_sources[0x41] 1475171 1 T1 28 T2 77 T3 7964
valid_sources[0x42] 1350257 1 T1 17 T2 78 T3 7756
valid_sources[0x43] 1515912 1 T1 58 T2 62 T3 7844
valid_sources[0x44] 1521721 1 T1 9 T2 57 T3 7920
valid_sources[0x45] 1353740 1 T1 48 T2 62 T3 7822
valid_sources[0x46] 2055867 1 T1 18 T2 66 T3 7851
valid_sources[0x47] 1348089 1 T1 21 T2 78 T3 7995
valid_sources[0x48] 1430968 1 T1 9 T2 68 T3 8021
valid_sources[0x49] 1477724 1 T1 17 T2 77 T3 8006
valid_sources[0x4a] 3893378 1 T1 19 T2 55 T3 7765
valid_sources[0x4b] 1557277 1 T1 6 T2 58 T3 7804
valid_sources[0x4c] 1349137 1 T1 25 T2 85 T3 7977
valid_sources[0x4d] 1352585 1 T1 24 T2 56 T3 7883
valid_sources[0x4e] 2051664 1 T1 36 T2 69 T3 7820
valid_sources[0x4f] 2212983 1 T1 17 T2 67 T3 8063
valid_sources[0x50] 1346379 1 T1 14 T2 56 T3 7998
valid_sources[0x51] 1794594 1 T1 6 T2 57 T3 7856
valid_sources[0x52] 3411316 1 T1 6 T2 57 T3 8166
valid_sources[0x53] 1367722 1 T1 21 T2 76 T3 7959
valid_sources[0x54] 1357522 1 T1 22 T2 59 T3 7823
valid_sources[0x55] 1349795 1 T1 10 T2 67 T3 7887
valid_sources[0x56] 1352829 1 T1 19 T2 74 T3 7784
valid_sources[0x57] 1346094 1 T1 10 T2 64 T3 7963
valid_sources[0x58] 1366947 1 T1 25 T2 82 T3 7986
valid_sources[0x59] 1355932 1 T1 39 T2 40 T3 7781
valid_sources[0x5a] 1347213 1 T1 20 T2 52 T3 8071
valid_sources[0x5b] 1793972 1 T1 41 T2 71 T3 7900
valid_sources[0x5c] 1346619 1 T1 14 T2 56 T3 7704
valid_sources[0x5d] 1356101 1 T1 47 T2 75 T3 7896
valid_sources[0x5e] 1355175 1 T1 12 T2 70 T3 7950
valid_sources[0x5f] 1568206 1 T1 32 T2 59 T3 7778
valid_sources[0x60] 1368724 1 T1 10 T2 52 T3 7879
valid_sources[0x61] 2276681 1 T1 9 T2 77 T3 7809
valid_sources[0x62] 1352326 1 T1 34 T2 61 T3 7829
valid_sources[0x63] 3388944 1 T1 48 T2 81 T3 7976
valid_sources[0x64] 1357380 1 T1 12 T2 66 T3 7947
valid_sources[0x65] 1347936 1 T1 43 T2 54 T3 7928
valid_sources[0x66] 1349237 1 T1 23 T2 56 T3 7825
valid_sources[0x67] 1348917 1 T1 10 T2 73 T3 7871
valid_sources[0x68] 1347325 1 T1 15 T2 63 T3 7815
valid_sources[0x69] 1830488 1 T1 26 T2 65 T3 7900
valid_sources[0x6a] 1356628 1 T1 17 T2 60 T3 7882
valid_sources[0x6b] 1354300 1 T1 46 T2 57 T3 7968
valid_sources[0x6c] 1418300 1 T1 37 T2 66 T3 7952
valid_sources[0x6d] 2203625 1 T1 31 T2 65 T3 7993
valid_sources[0x6e] 1344331 1 T1 12 T2 84 T3 7862
valid_sources[0x6f] 2464877 1 T1 16 T2 82 T3 7754
valid_sources[0x70] 2262872 1 T1 39 T2 44 T3 7973
valid_sources[0x71] 1344568 1 T1 13 T2 83 T3 7867
valid_sources[0x72] 1389105 1 T1 13 T2 59 T3 7788
valid_sources[0x73] 1357105 1 T1 12 T2 57 T3 7845
valid_sources[0x74] 1348536 1 T1 19 T2 65 T3 7874
valid_sources[0x75] 2222841 1 T1 8 T2 60 T3 7914
valid_sources[0x76] 1349810 1 T1 8 T2 73 T3 7853
valid_sources[0x77] 1544405 1 T1 14 T2 56 T3 7980
valid_sources[0x78] 1349264 1 T1 14 T2 51 T3 7793
valid_sources[0x79] 2233595 1 T1 19 T2 62 T3 7914
valid_sources[0x7a] 1353916 1 T1 22 T2 70 T3 8066
valid_sources[0x7b] 1355327 1 T1 9 T2 60 T3 8052
valid_sources[0x7c] 1343881 1 T1 31 T2 72 T3 7848
valid_sources[0x7d] 1353499 1 T1 8 T2 49 T3 7779
valid_sources[0x7e] 1350091 1 T1 15 T2 82 T3 7703
valid_sources[0x7f] 1453267 1 T1 22 T2 72 T3 7951
valid_sources[0x80] 1353629 1 T1 46 T2 71 T3 8108



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 87907279 1 T1 2166 T2 7719 T3 416074
values[0x0] all_enables biggest_size 61300950 1 T1 663 T2 1820 T3 255449
values[0x1] all_enables biggest_size 52701807 1 T1 607 T2 1682 T3 216730

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%