Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256922990

1

T1

1789

T2

5732

T3

113151

full_word

202025382

1

T1

3436

T2

11221

T3

888253

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458948052	1			T1	5225		T2	16953		T3	201976
auto[TlIntgErrCmd]	107	1			T108	8		T109	5		T110	7
auto[TlIntgErrData]	105	1			T108	8		T109	5		T110	6
auto[TlIntgErrBoth]	108	1			T108	4		T109	10		T110	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241302949

1

T1

3340

T2

11461

T3

109549

auto[1]

217645423

1

T1

1885

T2

5492

T3

924276

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153366615	1			T1	1174		T2	3742		T3	679418
auto[TlIntgErrNone]	partial	auto[1]	103556082	1			T1	615		T2	1990		T3	452097
auto[TlIntgErrNone]	full_word	auto[0]	87936183	1			T1	2166		T2	7719		T3	416074
auto[TlIntgErrNone]	full_word	auto[1]	114089172	1			T1	1270		T2	3502		T3	472179
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T108	4		T109	3		T110	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T108	4		T109	1		T110	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T168	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T109	1		T164	1		T169	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T108	4		T109	3		T110	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T108	2		T109	2		T110	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T108	1		T170	1		T166	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T108	1		T167	1		T164	2
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T108	1		T109	4		T110	4
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T108	2		T109	5		T110	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T110	1		T171	2		T172	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T108	1		T109	1		T164	2