Unified Coverage Report :: Module :: keccak_round

Module : keccak_round

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.39	65.98	100.00		26.67	79.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak	77.06	65.98	100.00		40.00	79.31	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.06	65.98	100.00		40.00	79.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.47	81.77	88.24	100.00	40.00	78.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak_p	81.25	100.00	75.00			50.00	100.00
u_prim_sec_anchor_buf	100.00	100.00
u_round_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
TOTAL		97	64	65.98
CONT_ASSIGN	177	0	0
ALWAYS	180	3	3	100.00
ALWAYS	186	67	35	52.24
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
ALWAYS	468	6	6	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	485	7	7	100.00
ALWAYS	507	4	3	75.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	551	0	0
ALWAYS	575	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
177		unreachable
180	3	3
186	1	1
188	1	1
189	1	1
190	1	1
192	1	1
193	1	1
195	1	1
196	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
206	1	1
208	1	1
210	1	1
212	1	1
214	1	1
215	1	1
216	1	1
221	1	1
223	1	1
224	1	1
226		unreachable
229		unreachable
230		unreachable
231	1	1
233	1	1
235	1	1
241	1	1
243	1	1
244		unreachable
246		unreachable
247		unreachable
249	1	1
251	1	1
260	0	1
261	0	1
272	0	1
273	0	1
274	0	1
275	0	1
278	0	1
281	0	1
282	0	1
284		unreachable
292	0	1
293	0	1
301	0	1
304	0	1
307	0	1
308	0	1
317	0	1
318	0	1
327	0	1
333	0	1
336	0	1
339	0	1
342	0	1
343	0	1
352	0	1
353	0	1
361	0	1
363	0	1
365		unreachable
367		unreachable
368		unreachable
371	0	1
373	0	1
376	0	1
377	0	1
382	0	1
387	1	1
388	1	1
400	1	1
401	1	1
			MISSING_ELSE
407	1	1
439	1	1
450	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
			MISSING_ELSE
477	1	1
485	1	1
486	1	1
487	1	1
488	1	1
492	1	1
493	1	1
496	1	1
			MISSING_ELSE
507	1	1
509	1	1
511	1	1
513	0	1
			MISSING_ELSE
			MISSING_ELSE
518	1	1
548	1	1
549	1	1
551		unreachable
575	1	1
576	1	1
578	1	1

---

Cond Coverage for Module : keccak_round

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       177
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       231
 EXPRESSION (((!EnMasking)) && run_i)
             -------1------    --2--

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T1,T2,T3

 LINE       272
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       450
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       450
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : keccak_round

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	3	37.50	(Not included in score)
Transitions	15	4	26.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	233	Covered	T1,T2,T3
KeccakStError	382	Not Covered
KeccakStIdle	212	Covered	T1,T2,T3
KeccakStPhase1	226	Not Covered
KeccakStPhase2Cycle1	273	Not Covered
KeccakStPhase2Cycle2	304	Not Covered
KeccakStPhase2Cycle3	339	Not Covered
KeccakStTerminalError	401	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
KeccakStActive->KeccakStIdle	244	Covered	T1,T2,T3
KeccakStActive->KeccakStTerminalError	401	Covered	T6,T7,T8
KeccakStError->KeccakStTerminalError	401	Not Covered
KeccakStIdle->KeccakStActive	233	Covered	T1,T2,T3
KeccakStIdle->KeccakStPhase1	226	Not Covered
KeccakStIdle->KeccakStTerminalError	401	Covered	T1,T4,T5
KeccakStPhase1->KeccakStPhase2Cycle1	273	Not Covered
KeccakStPhase1->KeccakStTerminalError	401	Not Covered
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	304	Not Covered
KeccakStPhase2Cycle1->KeccakStTerminalError	401	Not Covered
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	339	Not Covered
KeccakStPhase2Cycle2->KeccakStTerminalError	401	Not Covered
KeccakStPhase2Cycle3->KeccakStIdle	365	Not Covered
KeccakStPhase2Cycle3->KeccakStPhase1	371	Not Covered
KeccakStPhase2Cycle3->KeccakStTerminalError	401	Not Covered

---

Branch Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
Branches		29	23	79.31
TERNARY	450	2	2	100.00
IF	180	2	2	100.00
CASE	208	12	7	58.33
IF	400	2	2	100.00
IF	468	4	4	100.00
IF	486	2	2	100.00
IF	509	3	2	66.67
IF	575	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	450	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	208	case (keccak_st)
-2-:	210	if (valid_i)
-3-:	216	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	224	if ((EnMasking && run_i))
-5-:	231	if (((!EnMasking) && run_i))
-6-:	243	if (rnd_eq_end)
-7-:	272	if ((rand_early_i || rand_valid_i))
-8-:	363	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	Covered	T1,T2,T3
KeccakStIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
KeccakStIdle	0	0	1	-	-	-	-	Unreachable
KeccakStIdle	0	0	0	1	-	-	-	Covered	T1,T2,T3
KeccakStIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
KeccakStActive	-	-	-	-	1	-	-	Unreachable	T1,T2,T3
KeccakStActive	-	-	-	-	0	-	-	Covered	T1,T2,T3
KeccakStPhase1	-	-	-	-	-	1	-	Not Covered
KeccakStPhase1	-	-	-	-	-	0	-	Unreachable
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle3	-	-	-	-	-	-	1	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	0	Not Covered
KeccakStError	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	400	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	468	if ((!rst_n))
-2-:	470	if (rst_storage)
-3-:	472	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	486	if (xor_message)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	if (rst_storage)
-2-:	511	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	575	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keccak_round

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClearAssertStIdle_A	2147483647	349354	0	0
OneHot0ValidAndRun_A	2147483647	2147483647	0	0
ValidRunAssertStIdle_A	2147483647	56970341	0	0
WidthDivisableByDInWidth_A	1029	1029	0	0
gen_unmask_st_chk.UnmaskValidStates_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ClearAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349354	0	0
T1	69504	7	0	0
T2	177222	16	0	0
T3	214252	2265	0	0
T4	3894	0	0	0
T12	268060	378	0	0
T13	16321	9	0	0
T14	155359	66	0	0
T15	970506	390	0	0
T16	144793	2265	0	0
T17	349577	42	0	0
T18	0	109	0	0

OneHot0ValidAndRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69504	69364	0	0
T2	177222	177144	0	0
T3	214252	214251	0	0
T4	3894	3763	0	0
T12	268060	267977	0	0
T13	16321	16226	0	0
T14	155359	155284	0	0
T15	970506	970496	0	0
T16	144793	144793	0	0
T17	349577	349512	0	0

ValidRunAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	56970341	0	0
T1	69504	943	0	0
T2	177222	1912	0	0
T3	214252	234193	0	0
T4	3894	0	0	0
T12	268060	159865	0	0
T13	16321	638	0	0
T14	155359	6738	0	0
T15	970506	105298	0	0
T16	144793	234193	0	0
T17	349577	4265	0	0
T18	0	11107	0	0

WidthDivisableByDInWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

gen_unmask_st_chk.UnmaskValidStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69504	69364	0	0
T2	177222	177144	0	0
T3	214252	214251	0	0
T4	3894	3763	0	0
T12	268060	267977	0	0
T13	16321	16226	0	0
T14	155359	155284	0	0
T15	970506	970496	0	0
T16	144793	144793	0	0
T17	349577	349512	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69504	69364	0	0
T2	177222	177144	0	0
T3	214252	214251	0	0
T4	3894	3763	0	0
T12	268060	267977	0	0
T13	16321	16226	0	0
T14	155359	155284	0	0
T15	970506	970496	0	0
T16	144793	144793	0	0
T17	349577	349512	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak

	Line No.	Total	Covered	Percent
TOTAL		97	64	65.98
CONT_ASSIGN	177	0	0
ALWAYS	180	3	3	100.00
ALWAYS	186	67	35	52.24
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
ALWAYS	468	6	6	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	485	7	7	100.00
ALWAYS	507	4	3	75.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	551	0	0
ALWAYS	575	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
177		unreachable
180	3	3
186	1	1
188	1	1
189	1	1
190	1	1
192	1	1
193	1	1
195	1	1
196	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
206	1	1
208	1	1
210	1	1
212	1	1
214	1	1
215	1	1
216	1	1
221	1	1
223	1	1
224	1	1
226		unreachable
229		unreachable
230		unreachable
231	1	1
233	1	1
235	1	1
241	1	1
243	1	1
244		unreachable
246		unreachable
247		unreachable
249	1	1
251	1	1
260	0	1
261	0	1
272	0	1
273	0	1
274	0	1
275	0	1
278	0	1
281	0	1
282	0	1
284		unreachable
292	0	1
293	0	1
301	0	1
304	0	1
307	0	1
308	0	1
317	0	1
318	0	1
327	0	1
333	0	1
336	0	1
339	0	1
342	0	1
343	0	1
352	0	1
353	0	1
361	0	1
363	0	1
365		unreachable
367		unreachable
368		unreachable
371	0	1
373	0	1
376	0	1
377	0	1
382	0	1
387	1	1
388	1	1
400	1	1
401	1	1
			MISSING_ELSE
407	1	1
439	1	1
450	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
			MISSING_ELSE
477	1	1
485	1	1
486	1	1
487	1	1
488	1	1
492	1	1
493	1	1
496	1	1
			MISSING_ELSE
507	1	1
509	1	1
511	1	1
513	0	1
			MISSING_ELSE
			MISSING_ELSE
518	1	1
548	1	1
549	1	1
551		unreachable
575	1	1
576	1	1
578	1	1

---

Cond Coverage for Instance : tb.dut.u_sha3.u_keccak

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       177
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       231
 EXPRESSION (((!EnMasking)) && run_i)
             -------1------    --2--

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T1,T2,T3

 LINE       272
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       450
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       450
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sha3.u_keccak

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	3	37.50	(Not included in score)
Transitions	10	4	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	233	Covered	T1,T2,T3
KeccakStError	382	Excluded
KeccakStIdle	212	Covered	T1,T2,T3
KeccakStPhase1	226	Not Covered
KeccakStPhase2Cycle1	273	Not Covered
KeccakStPhase2Cycle2	304	Not Covered
KeccakStPhase2Cycle3	339	Not Covered
KeccakStTerminalError	401	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
KeccakStActive->KeccakStIdle	244	Covered	T1,T2,T3
KeccakStActive->KeccakStTerminalError	401	Covered	T6,T7,T8
KeccakStError->KeccakStTerminalError	401	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStIdle->KeccakStActive	233	Covered	T1,T2,T3
KeccakStIdle->KeccakStPhase1	226	Not Covered
KeccakStIdle->KeccakStTerminalError	401	Covered	T1,T4,T5
KeccakStPhase1->KeccakStPhase2Cycle1	273	Not Covered
KeccakStPhase1->KeccakStTerminalError	401	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	304	Not Covered
KeccakStPhase2Cycle1->KeccakStTerminalError	401	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	339	Not Covered
KeccakStPhase2Cycle2->KeccakStTerminalError	401	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStPhase2Cycle3->KeccakStIdle	365	Not Covered
KeccakStPhase2Cycle3->KeccakStPhase1	371	Not Covered
KeccakStPhase2Cycle3->KeccakStTerminalError	401	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak

	Line No.	Total	Covered	Percent
Branches		29	23	79.31
TERNARY	450	2	2	100.00
IF	180	2	2	100.00
CASE	208	12	7	58.33
IF	400	2	2	100.00
IF	468	4	4	100.00
IF	486	2	2	100.00
IF	509	3	2	66.67
IF	575	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	450	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	208	case (keccak_st)
-2-:	210	if (valid_i)
-3-:	216	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	224	if ((EnMasking && run_i))
-5-:	231	if (((!EnMasking) && run_i))
-6-:	243	if (rnd_eq_end)
-7-:	272	if ((rand_early_i || rand_valid_i))
-8-:	363	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	Covered	T1,T2,T3
KeccakStIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
KeccakStIdle	0	0	1	-	-	-	-	Unreachable
KeccakStIdle	0	0	0	1	-	-	-	Covered	T1,T2,T3
KeccakStIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
KeccakStActive	-	-	-	-	1	-	-	Unreachable	T1,T2,T3
KeccakStActive	-	-	-	-	0	-	-	Covered	T1,T2,T3
KeccakStPhase1	-	-	-	-	-	1	-	Not Covered
KeccakStPhase1	-	-	-	-	-	0	-	Unreachable
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle3	-	-	-	-	-	-	1	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	0	Not Covered
KeccakStError	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	400	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	468	if ((!rst_n))
-2-:	470	if (rst_storage)
-3-:	472	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	486	if (xor_message)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	if (rst_storage)
-2-:	511	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	575	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClearAssertStIdle_A	2147483647	349354	0	0
OneHot0ValidAndRun_A	2147483647	2147483647	0	0
ValidRunAssertStIdle_A	2147483647	56970341	0	0
WidthDivisableByDInWidth_A	1029	1029	0	0
gen_unmask_st_chk.UnmaskValidStates_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ClearAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349354	0	0
T1	69504	7	0	0
T2	177222	16	0	0
T3	214252	2265	0	0
T4	3894	0	0	0
T12	268060	378	0	0
T13	16321	9	0	0
T14	155359	66	0	0
T15	970506	390	0	0
T16	144793	2265	0	0
T17	349577	42	0	0
T18	0	109	0	0

OneHot0ValidAndRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69504	69364	0	0
T2	177222	177144	0	0
T3	214252	214251	0	0
T4	3894	3763	0	0
T12	268060	267977	0	0
T13	16321	16226	0	0
T14	155359	155284	0	0
T15	970506	970496	0	0
T16	144793	144793	0	0
T17	349577	349512	0	0

ValidRunAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	56970341	0	0
T1	69504	943	0	0
T2	177222	1912	0	0
T3	214252	234193	0	0
T4	3894	0	0	0
T12	268060	159865	0	0
T13	16321	638	0	0
T14	155359	6738	0	0
T15	970506	105298	0	0
T16	144793	234193	0	0
T17	349577	4265	0	0
T18	0	11107	0	0

WidthDivisableByDInWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

gen_unmask_st_chk.UnmaskValidStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69504	69364	0	0
T2	177222	177144	0	0
T3	214252	214251	0	0
T4	3894	3763	0	0
T12	268060	267977	0	0
T13	16321	16226	0	0
T14	155359	155284	0	0
T15	970506	970496	0	0
T16	144793	144793	0	0
T17	349577	349512	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69504	69364	0	0
T2	177222	177144	0	0
T3	214252	214251	0	0
T4	3894	3763	0	0
T12	268060	267977	0	0
T13	16321	16226	0	0
T14	155359	155284	0	0
T15	970506	970496	0	0
T16	144793	144793	0	0
T17	349577	349512	0	0