Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	424418	0	0
entropy_period_rd_A	2147483647	2170	0	0
intr_enable_rd_A	2147483647	2945	0	0
prefix_0_rd_A	2147483647	2291	0	0
prefix_10_rd_A	2147483647	2322	0	0
prefix_1_rd_A	2147483647	2447	0	0
prefix_2_rd_A	2147483647	2326	0	0
prefix_3_rd_A	2147483647	2167	0	0
prefix_4_rd_A	2147483647	2395	0	0
prefix_5_rd_A	2147483647	2409	0	0
prefix_6_rd_A	2147483647	2341	0	0
prefix_7_rd_A	2147483647	2380	0	0
prefix_8_rd_A	2147483647	2312	0	0
prefix_9_rd_A	2147483647	2299	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	424418	0	0
T20	76296	0	0	0
T39	876899	129478	0	0
T46	0	65911	0	0
T47	0	132826	0	0
T114	0	41348	0	0
T115	0	12304	0	0
T116	0	11583	0	0
T117	0	28236	0	0
T118	0	96	0	0
T119	0	4	0	0
T120	0	2	0	0
T121	434493	0	0	0
T122	21674	0	0	0
T123	21354	0	0	0
T124	930663	0	0	0
T125	184821	0	0	0
T126	471400	0	0	0
T127	331790	0	0	0
T128	170308	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2170	0	0
T91	2260	4	0	0
T92	12066	75	0	0
T95	2990	10	0	0
T109	21019	58	0	0
T137	10955	13	0	0
T138	1913	2	0	0
T139	4618	6	0	0
T140	48301	456	0	0
T141	4537	7	0	0
T142	3709	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2945	0	0
T91	2260	7	0	0
T95	2990	18	0	0
T112	931	4	0	0
T137	10955	60	0	0
T138	1913	3	0	0
T139	4618	5	0	0
T140	48301	491	0	0
T143	804	12	0	0
T144	1309	3	0	0
T145	1348	26	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2291	0	0
T91	2260	5	0	0
T92	12066	57	0	0
T95	2990	17	0	0
T109	21019	57	0	0
T137	10955	54	0	0
T138	1913	4	0	0
T139	4618	11	0	0
T140	48301	378	0	0
T141	4537	8	0	0
T146	2362	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2322	0	0
T91	2260	3	0	0
T92	12066	46	0	0
T95	2990	4	0	0
T109	21019	44	0	0
T137	10955	33	0	0
T138	1913	6	0	0
T139	4618	11	0	0
T140	48301	437	0	0
T141	4537	10	0	0
T142	3709	10	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2447	0	0
T92	12066	56	0	0
T95	2990	8	0	0
T109	21019	62	0	0
T137	10955	86	0	0
T139	4618	7	0	0
T140	48301	463	0	0
T141	4537	8	0	0
T146	2362	4	0	0
T147	10159	16	0	0
T148	11503	67	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2326	0	0
T91	2260	2	0	0
T92	12066	61	0	0
T95	2990	7	0	0
T109	21019	52	0	0
T137	10955	42	0	0
T138	1913	1	0	0
T139	4618	5	0	0
T140	48301	450	0	0
T141	4537	9	0	0
T142	3709	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2167	0	0
T91	2260	6	0	0
T92	12066	51	0	0
T95	2990	6	0	0
T109	21019	29	0	0
T137	10955	48	0	0
T138	1913	2	0	0
T139	4618	12	0	0
T140	48301	410	0	0
T141	4537	8	0	0
T142	3709	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T92	12066	51	0	0
T95	2990	10	0	0
T109	21019	17	0	0
T137	10955	64	0	0
T139	4618	10	0	0
T140	48301	447	0	0
T141	4537	9	0	0
T142	3709	5	0	0
T146	2362	4	0	0
T148	11503	64	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2409	0	0
T91	2260	5	0	0
T92	12066	49	0	0
T95	2990	12	0	0
T109	21019	37	0	0
T137	10955	39	0	0
T139	4618	11	0	0
T140	48301	441	0	0
T141	4537	3	0	0
T142	3709	14	0	0
T146	2362	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T91	2260	2	0	0
T92	12066	45	0	0
T109	21019	39	0	0
T137	10955	34	0	0
T138	1913	3	0	0
T139	4618	9	0	0
T140	48301	422	0	0
T141	4537	9	0	0
T146	2362	1	0	0
T147	10159	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2380	0	0
T91	2260	1	0	0
T92	12066	51	0	0
T95	2990	16	0	0
T109	21019	45	0	0
T137	10955	19	0	0
T138	1913	9	0	0
T139	4618	6	0	0
T140	48301	421	0	0
T141	4537	14	0	0
T146	2362	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2312	0	0
T91	2260	6	0	0
T92	12066	31	0	0
T95	2990	9	0	0
T109	21019	24	0	0
T137	10955	30	0	0
T139	4618	5	0	0
T140	48301	451	0	0
T141	4537	8	0	0
T142	3709	4	0	0
T146	2362	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2299	0	0
T91	2260	2	0	0
T92	12066	43	0	0
T95	2990	9	0	0
T109	21019	46	0	0
T137	10955	31	0	0
T139	4618	5	0	0
T140	48301	454	0	0
T141	4537	9	0	0
T142	3709	2	0	0
T147	10159	24	0	0