Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256416871

1

T1

2129

T2

111907

T3

27935

full_word

199616539

1

T1

12384

T2

889093

T3

45625

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456033140	1			T1	14513		T2	200816		T3	73560
auto[TlIntgErrCmd]	88	1			T93	4		T94	3		T95	3
auto[TlIntgErrData]	75	1			T93	1		T94	3		T95	5
auto[TlIntgErrBoth]	107	1			T93	5		T94	4		T95	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240650536

1

T1

9992

T2

109281

T3

49502

auto[1]

215382874

1

T1

4521

T2

915353

T3

24058

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153157473	1			T1	1179		T2	678762		T3	16899
auto[TlIntgErrNone]	partial	auto[1]	103259153	1			T1	950		T2	440311		T3	11036
auto[TlIntgErrNone]	full_word	auto[0]	87492933	1			T1	8813		T2	414051		T3	32603
auto[TlIntgErrNone]	full_word	auto[1]	112123581	1			T1	3571		T2	475042		T3	13022
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T93	2		T94	1		T153	3
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T93	1		T94	2		T95	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T154	1		T157	1		T155	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T93	1		T154	2		T159	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T93	1		T94	1		T95	3
auto[TlIntgErrData]	partial	auto[1]	31	1			T94	1		T95	2		T153	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T160	1		T161	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T94	1		T153	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T93	1		T94	1		T153	4
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T93	3		T94	3		T95	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T93	1		T154	1		T159	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T156	1		T162	1		T157	1