Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253726815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

201032977

1

T1

62388

T2

339690

T3

43889

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	240038240	1			T1	65568		T2	447145		T3	46177
values[0x0]	103099614	1			T1	13185		T2	204853		T3	10695
values[0x1]	111621938	1			T1	14301		T2	223840		T3	11394

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197667981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

257091811

1

T1

69182

T2

458170

T3

49202

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1390691	1			T1	352		T2	3445		T3	286
valid_sources[0x01]	1841975	1			T1	375		T2	3322		T3	250
valid_sources[0x02]	1375661	1			T1	333		T2	3294		T3	246
valid_sources[0x03]	2278491	1			T1	394		T2	3489		T3	276
valid_sources[0x04]	4466011	1			T1	342		T2	3384		T3	254
valid_sources[0x05]	1376421	1			T1	366		T2	3393		T3	254
valid_sources[0x06]	1382816	1			T1	372		T2	3547		T3	226
valid_sources[0x07]	1365475	1			T1	345		T2	3188		T3	229
valid_sources[0x08]	1383676	1			T1	323		T2	3209		T3	235
valid_sources[0x09]	2276685	1			T1	354		T2	3401		T3	288
valid_sources[0x0a]	1568487	1			T1	343		T2	3440		T3	252
valid_sources[0x0b]	1390598	1			T1	379		T2	3314		T3	251
valid_sources[0x0c]	1719919	1			T1	356		T2	3455		T3	261
valid_sources[0x0d]	1414732	1			T1	348		T2	3567		T3	303
valid_sources[0x0e]	1407186	1			T1	351		T2	3548		T3	284
valid_sources[0x0f]	1373692	1			T1	392		T2	3449		T3	277
valid_sources[0x10]	1390507	1			T1	364		T2	3534		T3	294
valid_sources[0x11]	1380496	1			T1	320		T2	3407		T3	244
valid_sources[0x12]	1382568	1			T1	409		T2	3487		T3	264
valid_sources[0x13]	1379952	1			T1	349		T2	3570		T3	250
valid_sources[0x14]	1380284	1			T1	366		T2	3570		T3	283
valid_sources[0x15]	1377657	1			T1	326		T2	3280		T3	225
valid_sources[0x16]	1392091	1			T1	372		T2	3601		T3	289
valid_sources[0x17]	1866797	1			T1	412		T2	3345		T3	259
valid_sources[0x18]	1504338	1			T1	360		T2	3436		T3	239
valid_sources[0x19]	1377956	1			T1	353		T2	3358		T3	245
valid_sources[0x1a]	1375173	1			T1	382		T2	3355		T3	273
valid_sources[0x1b]	1668451	1			T1	320		T2	3424		T3	264
valid_sources[0x1c]	2747980	1			T1	325		T2	3428		T3	269
valid_sources[0x1d]	2292177	1			T1	336		T2	3452		T3	257
valid_sources[0x1e]	1424421	1			T1	373		T2	3439		T3	263
valid_sources[0x1f]	3442816	1			T1	347		T2	3372		T3	270
valid_sources[0x20]	2043074	1			T1	382		T2	3373		T3	264
valid_sources[0x21]	1441741	1			T1	369		T2	3260		T3	257
valid_sources[0x22]	1380118	1			T1	392		T2	3403		T3	257
valid_sources[0x23]	3401171	1			T1	399		T2	3444		T3	258
valid_sources[0x24]	1378131	1			T1	385		T2	3349		T3	270
valid_sources[0x25]	1377792	1			T1	335		T2	3622		T3	243
valid_sources[0x26]	1388307	1			T1	388		T2	3366		T3	257
valid_sources[0x27]	2289244	1			T1	371		T2	3387		T3	286
valid_sources[0x28]	1374567	1			T1	362		T2	3402		T3	304
valid_sources[0x29]	1704589	1			T1	321		T2	3662		T3	274
valid_sources[0x2a]	1511313	1			T1	340		T2	3515		T3	276
valid_sources[0x2b]	1376356	1			T1	368		T2	3213		T3	246
valid_sources[0x2c]	3245838	1			T1	356		T2	3394		T3	284
valid_sources[0x2d]	1377641	1			T1	344		T2	3315		T3	312
valid_sources[0x2e]	1470042	1			T1	346		T2	3466		T3	229
valid_sources[0x2f]	1376853	1			T1	384		T2	3635		T3	252
valid_sources[0x30]	1832555	1			T1	345		T2	3572		T3	245
valid_sources[0x31]	1549680	1			T1	370		T2	3435		T3	299
valid_sources[0x32]	2594338	1			T1	400		T2	3342		T3	278
valid_sources[0x33]	1377421	1			T1	364		T2	3275		T3	300
valid_sources[0x34]	1381878	1			T1	368		T2	3229		T3	249
valid_sources[0x35]	1380961	1			T1	380		T2	3308		T3	262
valid_sources[0x36]	1379732	1			T1	366		T2	3435		T3	259
valid_sources[0x37]	1392355	1			T1	346		T2	3292		T3	264
valid_sources[0x38]	1516049	1			T1	315		T2	3358		T3	269
valid_sources[0x39]	1379290	1			T1	394		T2	3417		T3	282
valid_sources[0x3a]	1377267	1			T1	350		T2	3265		T3	254
valid_sources[0x3b]	1390027	1			T1	378		T2	3725		T3	255
valid_sources[0x3c]	1387143	1			T1	397		T2	3304		T3	232
valid_sources[0x3d]	1378554	1			T1	354		T2	3587		T3	263
valid_sources[0x3e]	1374658	1			T1	388		T2	3557		T3	245
valid_sources[0x3f]	2324062	1			T1	344		T2	3416		T3	265
valid_sources[0x40]	1381134	1			T1	358		T2	3366		T3	246
valid_sources[0x41]	1374793	1			T1	372		T2	3337		T3	245
valid_sources[0x42]	1373130	1			T1	371		T2	3460		T3	303
valid_sources[0x43]	1454491	1			T1	389		T2	3357		T3	257
valid_sources[0x44]	1388840	1			T1	383		T2	3318		T3	260
valid_sources[0x45]	1873509	1			T1	357		T2	3618		T3	262
valid_sources[0x46]	1372943	1			T1	385		T2	3541		T3	281
valid_sources[0x47]	1381016	1			T1	315		T2	3413		T3	272
valid_sources[0x48]	1506183	1			T1	380		T2	3488		T3	232
valid_sources[0x49]	1375791	1			T1	346		T2	3350		T3	255
valid_sources[0x4a]	1382840	1			T1	360		T2	3524		T3	249
valid_sources[0x4b]	1376383	1			T1	397		T2	3412		T3	274
valid_sources[0x4c]	3445683	1			T1	369		T2	3342		T3	280
valid_sources[0x4d]	1369214	1			T1	373		T2	3295		T3	283
valid_sources[0x4e]	1380077	1			T1	330		T2	3318		T3	246
valid_sources[0x4f]	1374303	1			T1	318		T2	3557		T3	257
valid_sources[0x50]	2236258	1			T1	386		T2	3480		T3	282
valid_sources[0x51]	1384064	1			T1	336		T2	3284		T3	267
valid_sources[0x52]	1530958	1			T1	347		T2	3340		T3	275
valid_sources[0x53]	1375234	1			T1	356		T2	3314		T3	276
valid_sources[0x54]	1375336	1			T1	374		T2	3256		T3	276
valid_sources[0x55]	1393778	1			T1	340		T2	3226		T3	267
valid_sources[0x56]	1393379	1			T1	327		T2	3336		T3	285
valid_sources[0x57]	2096090	1			T1	377		T2	3191		T3	238
valid_sources[0x58]	3783829	1			T1	380		T2	3416		T3	260
valid_sources[0x59]	2241995	1			T1	378		T2	3398		T3	264
valid_sources[0x5a]	1409161	1			T1	345		T2	3346		T3	261
valid_sources[0x5b]	1436767	1			T1	412		T2	3277		T3	271
valid_sources[0x5c]	1454565	1			T1	327		T2	3629		T3	260
valid_sources[0x5d]	1509792	1			T1	376		T2	3256		T3	281
valid_sources[0x5e]	1378026	1			T1	345		T2	3563		T3	248
valid_sources[0x5f]	1839114	1			T1	397		T2	3516		T3	265
valid_sources[0x60]	1377565	1			T1	337		T2	3550		T3	270
valid_sources[0x61]	1444065	1			T1	357		T2	3366		T3	277
valid_sources[0x62]	1572115	1			T1	343		T2	3476		T3	329
valid_sources[0x63]	3609627	1			T1	343		T2	3673		T3	271
valid_sources[0x64]	1383395	1			T1	350		T2	3371		T3	267
valid_sources[0x65]	2295287	1			T1	365		T2	3383		T3	291
valid_sources[0x66]	2058873	1			T1	382		T2	3411		T3	286
valid_sources[0x67]	1396790	1			T1	417		T2	3390		T3	283
valid_sources[0x68]	3779568	1			T1	330		T2	3563		T3	277
valid_sources[0x69]	1464640	1			T1	375		T2	3372		T3	230
valid_sources[0x6a]	1381066	1			T1	354		T2	3383		T3	268
valid_sources[0x6b]	3783535	1			T1	359		T2	3566		T3	257
valid_sources[0x6c]	1387556	1			T1	389		T2	3251		T3	238
valid_sources[0x6d]	1380528	1			T1	370		T2	3593		T3	281
valid_sources[0x6e]	1483735	1			T1	368		T2	3300		T3	261
valid_sources[0x6f]	1856895	1			T1	404		T2	3204		T3	262
valid_sources[0x70]	2256001	1			T1	339		T2	3454		T3	247
valid_sources[0x71]	1383696	1			T1	339		T2	3345		T3	285
valid_sources[0x72]	1381989	1			T1	363		T2	3338		T3	280
valid_sources[0x73]	1379965	1			T1	368		T2	3329		T3	260
valid_sources[0x74]	1380522	1			T1	380		T2	3372		T3	263
valid_sources[0x75]	1378099	1			T1	361		T2	3268		T3	241
valid_sources[0x76]	1438771	1			T1	340		T2	3374		T3	271
valid_sources[0x77]	1381246	1			T1	366		T2	3433		T3	242
valid_sources[0x78]	2174494	1			T1	355		T2	3327		T3	265
valid_sources[0x79]	1466511	1			T1	391		T2	3447		T3	250
valid_sources[0x7a]	1384639	1			T1	363		T2	3395		T3	250
valid_sources[0x7b]	1384617	1			T1	351		T2	3382		T3	297
valid_sources[0x7c]	1374091	1			T1	375		T2	3547		T3	261
valid_sources[0x7d]	1832633	1			T1	365		T2	3316		T3	283
valid_sources[0x7e]	1383551	1			T1	371		T2	3386		T3	287
valid_sources[0x7f]	2273638	1			T1	379		T2	3494		T3	277
valid_sources[0x80]	1379739	1			T1	421		T2	3500		T3	281

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87943002

1

T1

46997

T2

128669

T3

31202

values[0x0]

all_enables

biggest_size

60817234

1

T1

8151

T2

114471

T3

6797

values[0x1]

all_enables

biggest_size

52272741

1

T1

7240

T2

96550

T3

5890