Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257805078

1

T1

30666

T2

536148

T3

24377

full_word

201291138

1

T1

62388

T2

339690

T3

43889

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459095926	1			T1	93054		T2	875838		T3	68266
auto[TlIntgErrCmd]	100	1			T106	3		T107	4		T108	2
auto[TlIntgErrData]	103	1			T106	4		T107	4		T108	5
auto[TlIntgErrBoth]	87	1			T106	3		T107	2		T108	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240826812

1

T1

65568

T2

447145

T3

46177

auto[1]

218269404

1

T1

27486

T2

428693

T3

22089

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152819302	1			T1	18571		T2	318476		T3	14975
auto[TlIntgErrNone]	partial	auto[1]	104985501	1			T1	12095		T2	217672		T3	9402
auto[TlIntgErrNone]	full_word	auto[0]	88007380	1			T1	46997		T2	128669		T3	31202
auto[TlIntgErrNone]	full_word	auto[1]	113283743	1			T1	15391		T2	211021		T3	12687
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T106	1		T107	2		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T106	2		T107	2		T108	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T165	1		T166	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T167	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T106	1		T107	2		T108	2
auto[TlIntgErrData]	partial	auto[1]	55	1			T106	2		T107	2		T108	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T165	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T106	1		T162	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T107	2		T108	1		T131	4
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T106	2		T108	2		T131	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T106	1		T168	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T161	1		T166	1		-	-