Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	946535	0	0
entropy_period_rd_A	2147483647	2084	0	0
intr_enable_rd_A	2147483647	2746	0	0
prefix_0_rd_A	2147483647	1889	0	0
prefix_10_rd_A	2147483647	1850	0	0
prefix_1_rd_A	2147483647	1885	0	0
prefix_2_rd_A	2147483647	1875	0	0
prefix_3_rd_A	2147483647	1850	0	0
prefix_4_rd_A	2147483647	1824	0	0
prefix_5_rd_A	2147483647	1894	0	0
prefix_6_rd_A	2147483647	1774	0	0
prefix_7_rd_A	2147483647	1818	0	0
prefix_8_rd_A	2147483647	1839	0	0
prefix_9_rd_A	2147483647	1784	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	946535	0	0
T18	497522	77182	0	0
T19	79134	0	0	0
T23	247410	0	0	0
T28	444339	0	0	0
T29	711067	0	0	0
T44	1545	0	0	0
T47	0	42892	0	0
T48	0	143961	0	0
T80	0	42454	0	0
T81	0	24054	0	0
T82	614541	0	0	0
T83	375436	0	0	0
T84	171434	0	0	0
T85	64233	0	0	0
T112	0	65183	0	0
T113	0	39617	0	0
T114	0	79048	0	0
T115	0	35448	0	0
T116	0	52692	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2084	0	0
T47	466422	67	0	0
T79	206216	0	0	0
T81	0	59	0	0
T92	0	4	0	0
T106	0	80	0	0
T128	0	7	0	0
T129	0	17	0	0
T130	0	21	0	0
T131	0	142	0	0
T132	0	58	0	0
T133	0	18	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2746	0	0
T47	466422	116	0	0
T79	206216	0	0	0
T81	0	52	0	0
T106	0	123	0	0
T111	0	11	0	0
T128	0	7	0	0
T129	0	24	0	0
T130	0	26	0	0
T131	0	169	0	0
T132	0	79	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0
T142	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1889	0	0
T47	466422	92	0	0
T79	206216	0	0	0
T81	0	54	0	0
T92	0	7	0	0
T106	0	48	0	0
T128	0	3	0	0
T129	0	12	0	0
T130	0	13	0	0
T131	0	80	0	0
T132	0	42	0	0
T133	0	6	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1850	0	0
T47	466422	110	0	0
T79	206216	0	0	0
T81	0	60	0	0
T92	0	13	0	0
T106	0	52	0	0
T128	0	9	0	0
T129	0	9	0	0
T130	0	19	0	0
T131	0	78	0	0
T132	0	48	0	0
T133	0	9	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T47	466422	111	0	0
T79	206216	0	0	0
T81	0	64	0	0
T92	0	4	0	0
T106	0	36	0	0
T129	0	13	0	0
T130	0	20	0	0
T131	0	89	0	0
T132	0	48	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0
T143	0	25	0	0
T144	0	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1875	0	0
T47	466422	118	0	0
T79	206216	0	0	0
T81	0	46	0	0
T92	0	1	0	0
T106	0	50	0	0
T128	0	5	0	0
T129	0	11	0	0
T130	0	25	0	0
T131	0	85	0	0
T132	0	34	0	0
T133	0	7	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1850	0	0
T47	466422	95	0	0
T79	206216	0	0	0
T81	0	43	0	0
T92	0	8	0	0
T106	0	31	0	0
T128	0	3	0	0
T129	0	11	0	0
T130	0	21	0	0
T131	0	85	0	0
T132	0	53	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0
T143	0	13	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1824	0	0
T47	466422	91	0	0
T79	206216	0	0	0
T81	0	60	0	0
T106	0	42	0	0
T129	0	10	0	0
T130	0	12	0	0
T131	0	79	0	0
T132	0	46	0	0
T133	0	1	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0
T143	0	37	0	0
T144	0	15	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1894	0	0
T47	466422	126	0	0
T79	206216	0	0	0
T81	0	86	0	0
T92	0	9	0	0
T106	0	35	0	0
T128	0	9	0	0
T129	0	8	0	0
T130	0	11	0	0
T131	0	95	0	0
T132	0	34	0	0
T133	0	3	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T47	466422	94	0	0
T79	206216	0	0	0
T81	0	52	0	0
T92	0	2	0	0
T106	0	33	0	0
T128	0	14	0	0
T129	0	8	0	0
T130	0	11	0	0
T131	0	76	0	0
T132	0	42	0	0
T133	0	2	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1818	0	0
T47	466422	83	0	0
T79	206216	0	0	0
T81	0	87	0	0
T92	0	6	0	0
T106	0	33	0	0
T128	0	9	0	0
T129	0	9	0	0
T130	0	17	0	0
T131	0	62	0	0
T132	0	39	0	0
T133	0	1	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T47	466422	111	0	0
T79	206216	0	0	0
T81	0	62	0	0
T92	0	1	0	0
T106	0	48	0	0
T128	0	6	0	0
T129	0	6	0	0
T130	0	24	0	0
T131	0	80	0	0
T132	0	53	0	0
T133	0	3	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1784	0	0
T47	466422	80	0	0
T79	206216	0	0	0
T81	0	78	0	0
T92	0	2	0	0
T106	0	49	0	0
T128	0	3	0	0
T129	0	9	0	0
T130	0	14	0	0
T131	0	74	0	0
T132	0	33	0	0
T133	0	4	0	0
T134	933	0	0	0
T135	22317	0	0	0
T136	804130	0	0	0
T137	462141	0	0	0
T138	512427	0	0	0
T139	173259	0	0	0
T140	941	0	0	0
T141	720342	0	0	0