Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256524197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200592923

1

T1

122605

T2

261285

T3

359226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	241466456	1			T1	131539		T2	347953		T3	464821
values[0x0]	103591595	1			T1	31052		T2	157761		T3	214471
values[0x1]	112059069	1			T1	33214		T2	173659		T3	231494

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199972007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

257145113

1

T1

139192

T2

354572

T3

479312

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1298373	1			T1	909		T3	3396		T12	19
valid_sources[0x01]	1297894	1			T1	742		T3	3334		T12	1
valid_sources[0x02]	1290017	1			T1	803		T3	3705		T12	2
valid_sources[0x03]	1296664	1			T1	748		T3	3495		T12	6
valid_sources[0x04]	2307249	1			T1	751		T3	3651		T12	13
valid_sources[0x05]	1303646	1			T1	732		T3	3450		T12	3
valid_sources[0x06]	1300769	1			T1	863		T3	3467		T14	4449
valid_sources[0x07]	1299008	1			T1	632		T3	3371		T12	12
valid_sources[0x08]	1295278	1			T1	752		T3	3618		T12	8
valid_sources[0x09]	1295430	1			T1	858		T3	3642		T12	9
valid_sources[0x0a]	1292062	1			T1	800		T3	3463		T13	6
valid_sources[0x0b]	1295340	1			T1	872		T3	3508		T12	18
valid_sources[0x0c]	1295730	1			T1	781		T3	3432		T12	1
valid_sources[0x0d]	1330239	1			T1	704		T3	3508		T12	27
valid_sources[0x0e]	2231409	1			T1	956		T3	3684		T12	9
valid_sources[0x0f]	2238345	1			T1	680		T3	3572		T12	36
valid_sources[0x10]	1300635	1			T1	686		T3	3503		T12	3
valid_sources[0x11]	1292582	1			T1	641		T3	3579		T12	7
valid_sources[0x12]	1295345	1			T1	603		T3	3654		T12	18
valid_sources[0x13]	1352503	1			T1	795		T3	3582		T12	4
valid_sources[0x14]	2138576	1			T1	759		T3	3563		T12	9
valid_sources[0x15]	1293583	1			T1	794		T3	3531		T12	9
valid_sources[0x16]	1297827	1			T1	792		T3	3683		T12	1
valid_sources[0x17]	1304469	1			T1	723		T3	3618		T12	3
valid_sources[0x18]	1289324	1			T1	746		T3	3480		T12	15
valid_sources[0x19]	3864870	1			T1	671		T3	3528		T12	6
valid_sources[0x1a]	1292985	1			T1	649		T3	3529		T12	18
valid_sources[0x1b]	1299811	1			T1	828		T3	3495		T12	9
valid_sources[0x1c]	1293348	1			T1	776		T3	3587		T12	3
valid_sources[0x1d]	1753089	1			T1	648		T3	3523		T14	4523
valid_sources[0x1e]	2223973	1			T1	726		T3	3574		T12	5
valid_sources[0x1f]	1337845	1			T1	876		T3	3582		T12	1
valid_sources[0x20]	1291516	1			T1	926		T3	3596		T13	35
valid_sources[0x21]	1292711	1			T1	761		T3	3443		T12	27
valid_sources[0x22]	1292470	1			T1	683		T3	3620		T12	5
valid_sources[0x23]	1304181	1			T1	680		T3	3374		T12	4
valid_sources[0x24]	1301242	1			T1	680		T3	3544		T12	3
valid_sources[0x25]	3811892	1			T1	717		T3	3319		T12	17
valid_sources[0x26]	3364408	1			T1	789		T3	3500		T12	10
valid_sources[0x27]	1289504	1			T1	783		T3	3503		T12	2
valid_sources[0x28]	1288023	1			T1	678		T3	3594		T12	19
valid_sources[0x29]	1412140	1			T1	873		T3	3554		T12	2
valid_sources[0x2a]	1300206	1			T1	736		T3	3581		T12	2
valid_sources[0x2b]	4927504	1			T1	689		T3	3676		T12	15
valid_sources[0x2c]	1312128	1			T1	782		T3	3606		T13	1
valid_sources[0x2d]	1297562	1			T1	699		T3	3685		T13	5
valid_sources[0x2e]	1289999	1			T1	917		T3	3574		T12	10
valid_sources[0x2f]	1316467	1			T1	742		T3	3474		T12	27
valid_sources[0x30]	1303317	1			T1	896		T3	3632		T12	8
valid_sources[0x31]	2182107	1			T1	744		T3	3594		T12	3
valid_sources[0x32]	1293518	1			T1	820		T3	3631		T13	1
valid_sources[0x33]	1432133	1			T1	867		T3	3575		T12	23
valid_sources[0x34]	1305376	1			T1	776		T3	3603		T14	4420
valid_sources[0x35]	1295843	1			T1	739		T3	3707		T12	12
valid_sources[0x36]	4557611	1			T1	775		T3	3452		T12	17
valid_sources[0x37]	1290739	1			T1	797		T3	3574		T13	2
valid_sources[0x38]	1302509	1			T1	697		T3	3581		T12	10
valid_sources[0x39]	1291985	1			T1	721		T3	3504		T12	22
valid_sources[0x3a]	1291099	1			T1	816		T3	3591		T13	21
valid_sources[0x3b]	1297869	1			T1	760		T3	3484		T12	9
valid_sources[0x3c]	2228935	1			T1	811		T3	3477		T12	3
valid_sources[0x3d]	1399391	1			T1	703		T3	3685		T13	44
valid_sources[0x3e]	1300362	1			T1	796		T3	3570		T12	3
valid_sources[0x3f]	2454562	1			T1	656		T3	3522		T12	6
valid_sources[0x40]	1313007	1			T1	906		T3	3500		T12	2
valid_sources[0x41]	1940282	1			T1	693		T3	3480		T12	22
valid_sources[0x42]	1481659	1			T1	836		T3	3447		T12	2
valid_sources[0x43]	2180270	1			T1	722		T3	3445		T14	4428
valid_sources[0x44]	2419875	1			T1	776		T3	3512		T14	4477
valid_sources[0x45]	1301098	1			T1	757		T3	3590		T13	13
valid_sources[0x46]	1299127	1			T1	753		T3	3482		T12	11
valid_sources[0x47]	1289826	1			T1	697		T3	3484		T12	23
valid_sources[0x48]	1315622	1			T1	697		T3	3466		T14	4544
valid_sources[0x49]	1984853	1			T1	862		T2	679373		T3	3496
valid_sources[0x4a]	1319176	1			T1	642		T3	3693		T12	43
valid_sources[0x4b]	1296803	1			T1	591		T3	3495		T12	9
valid_sources[0x4c]	2342478	1			T1	761		T3	3720		T12	6
valid_sources[0x4d]	1753778	1			T1	858		T3	3526		T13	49
valid_sources[0x4e]	1294044	1			T1	689		T3	3576		T12	7
valid_sources[0x4f]	4734034	1			T1	757		T3	3522		T13	10
valid_sources[0x50]	1300690	1			T1	765		T3	3462		T13	53
valid_sources[0x51]	2276061	1			T1	656		T3	3681		T12	3
valid_sources[0x52]	3382082	1			T1	823		T3	3584		T13	16
valid_sources[0x53]	1292839	1			T1	802		T3	3633		T12	9
valid_sources[0x54]	3704585	1			T1	689		T3	3524		T14	4519
valid_sources[0x55]	1316161	1			T1	830		T3	3443		T13	2
valid_sources[0x56]	1299493	1			T1	674		T3	3560		T12	2
valid_sources[0x57]	3793202	1			T1	663		T3	3469		T13	7
valid_sources[0x58]	1425913	1			T1	728		T3	3678		T12	20
valid_sources[0x59]	3557789	1			T1	699		T3	3610		T12	12
valid_sources[0x5a]	3737087	1			T1	660		T3	3568		T12	4
valid_sources[0x5b]	1293133	1			T1	696		T3	3754		T12	26
valid_sources[0x5c]	1294176	1			T1	735		T3	3718		T12	5
valid_sources[0x5d]	2191487	1			T1	837		T3	3535		T12	15
valid_sources[0x5e]	1303392	1			T1	783		T3	3531		T12	1
valid_sources[0x5f]	1291103	1			T1	733		T3	3632		T12	22
valid_sources[0x60]	3656888	1			T1	788		T3	3565		T12	7
valid_sources[0x61]	1303228	1			T1	692		T3	3521		T13	5
valid_sources[0x62]	1306738	1			T1	801		T3	3436		T12	2
valid_sources[0x63]	3364652	1			T1	747		T3	3360		T12	30
valid_sources[0x64]	1297762	1			T1	725		T3	3732		T12	11
valid_sources[0x65]	1479061	1			T1	727		T3	3596		T13	4
valid_sources[0x66]	1300309	1			T1	773		T3	3679		T12	1
valid_sources[0x67]	1296594	1			T1	766		T3	3688		T13	11
valid_sources[0x68]	3401566	1			T1	957		T3	3652		T12	6
valid_sources[0x69]	3791961	1			T1	791		T3	3619		T12	20
valid_sources[0x6a]	1302108	1			T1	768		T3	3604		T14	4566
valid_sources[0x6b]	1302291	1			T1	766		T3	3482		T12	2
valid_sources[0x6c]	1304092	1			T1	693		T3	3500		T12	19
valid_sources[0x6d]	1886960	1			T1	834		T3	3505		T12	7
valid_sources[0x6e]	1619319	1			T1	687		T3	3565		T12	11
valid_sources[0x6f]	1476543	1			T1	691		T3	3553		T12	2
valid_sources[0x70]	1410286	1			T1	740		T3	3467		T12	5
valid_sources[0x71]	1560935	1			T1	839		T3	3529		T14	4505
valid_sources[0x72]	3501311	1			T1	766		T3	3681		T12	11
valid_sources[0x73]	1293496	1			T1	793		T3	3528		T12	22
valid_sources[0x74]	1308572	1			T1	697		T3	3493		T12	9
valid_sources[0x75]	1973923	1			T1	627		T3	3704		T13	23
valid_sources[0x76]	2186539	1			T1	774		T3	3621		T13	1
valid_sources[0x77]	1995856	1			T1	696		T3	3681		T12	22
valid_sources[0x78]	1296997	1			T1	741		T3	3505		T12	1
valid_sources[0x79]	1301366	1			T1	661		T3	3483		T12	7
valid_sources[0x7a]	1295280	1			T1	640		T3	3459		T13	10
valid_sources[0x7b]	1431648	1			T1	772		T3	3537		T12	15
valid_sources[0x7c]	3717671	1			T1	691		T3	3776		T12	21
valid_sources[0x7d]	1302417	1			T1	780		T3	3546		T13	23
valid_sources[0x7e]	1421309	1			T1	631		T3	3583		T12	5
valid_sources[0x7f]	1292741	1			T1	692		T3	3605		T12	2
valid_sources[0x80]	1294891	1			T1	752		T3	3620		T12	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87705042

1

T1

87085

T2

101625

T3

133429

values[0x0]

all_enables

biggest_size

60763624

1

T1

19050

T2

86620

T3

122412

values[0x1]

all_enables

biggest_size

52124257

1

T1

16470

T2

73040

T3

103385