Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257511115

1

T1

73200

T2

418088

T3

551560

full_word

200655028

1

T1

122605

T2

261285

T3

359226

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458165853	1			T1	195805		T2	679373		T3	910786
auto[TlIntgErrCmd]	102	1			T110	10		T111	4		T112	4
auto[TlIntgErrData]	86	1			T110	6		T111	1		T112	2
auto[TlIntgErrBoth]	102	1			T110	4		T111	5		T112	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241660229

1

T1

131539

T2

347953

T3

464821

auto[1]

216505914

1

T1

64266

T2

331420

T3

445965

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153939233	1			T1	44454		T2	246328		T3	331392
auto[TlIntgErrNone]	partial	auto[1]	103571609	1			T1	28746		T2	171760		T3	220168
auto[TlIntgErrNone]	full_word	auto[0]	87720854	1			T1	87085		T2	101625		T3	133429
auto[TlIntgErrNone]	full_word	auto[1]	112934157	1			T1	35520		T2	159660		T3	225797
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T110	4		T112	4		T154	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T110	6		T111	4		T154	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T155	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T154	1		T156	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T110	3		T112	2		T154	5
auto[TlIntgErrData]	partial	auto[1]	28	1			T110	3		T111	1		T154	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T157	1		T158	1		T155	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T154	1		T159	1		T160	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T110	3		T111	2		T112	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T110	1		T111	3		T112	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T152	1		T161	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T155	1		T162	1		T163	1