Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	227061	0	0
entropy_period_rd_A	2147483647	1826	0	0
intr_enable_rd_A	2147483647	2564	0	0
prefix_0_rd_A	2147483647	1505	0	0
prefix_10_rd_A	2147483647	1628	0	0
prefix_1_rd_A	2147483647	1538	0	0
prefix_2_rd_A	2147483647	1603	0	0
prefix_3_rd_A	2147483647	1696	0	0
prefix_4_rd_A	2147483647	1607	0	0
prefix_5_rd_A	2147483647	1525	0	0
prefix_6_rd_A	2147483647	1502	0	0
prefix_7_rd_A	2147483647	1608	0	0
prefix_8_rd_A	2147483647	1550	0	0
prefix_9_rd_A	2147483647	1613	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	227061	0	0
T24	251668	23541	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	24600	0	0
T55	0	32509	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	9465	0	0
T110	0	4	0	0
T111	0	1	0	0
T116	0	74601	0	0
T117	0	41868	0	0
T118	0	17217	0	0
T119	0	205	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1826	0	0
T24	251668	27	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	106	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	54	0	0
T90	0	5	0	0
T110	0	132	0	0
T111	0	20	0	0
T112	0	55	0	0
T113	0	2	0	0
T130	0	21	0	0
T131	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T24	251668	46	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	55	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	34	0	0
T90	0	6	0	0
T110	0	191	0	0
T111	0	40	0	0
T112	0	106	0	0
T113	0	3	0	0
T130	0	27	0	0
T132	0	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1505	0	0
T24	251668	30	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	55	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	52	0	0
T90	0	15	0	0
T110	0	98	0	0
T111	0	14	0	0
T112	0	36	0	0
T113	0	1	0	0
T130	0	25	0	0
T132	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1628	0	0
T24	251668	37	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	49	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	41	0	0
T90	0	18	0	0
T110	0	96	0	0
T111	0	9	0	0
T112	0	38	0	0
T113	0	12	0	0
T130	0	15	0	0
T132	0	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T24	251668	23	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	89	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	41	0	0
T90	0	8	0	0
T110	0	75	0	0
T111	0	21	0	0
T112	0	39	0	0
T113	0	6	0	0
T130	0	24	0	0
T132	0	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1603	0	0
T24	251668	36	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	61	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	36	0	0
T90	0	10	0	0
T110	0	78	0	0
T111	0	28	0	0
T112	0	37	0	0
T113	0	5	0	0
T130	0	22	0	0
T132	0	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1696	0	0
T24	251668	63	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	126	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	30	0	0
T90	0	11	0	0
T110	0	96	0	0
T111	0	25	0	0
T112	0	34	0	0
T113	0	4	0	0
T130	0	13	0	0
T132	0	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607	0	0
T24	251668	22	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	79	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	50	0	0
T90	0	8	0	0
T110	0	72	0	0
T111	0	24	0	0
T112	0	35	0	0
T113	0	4	0	0
T130	0	18	0	0
T132	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T24	251668	22	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	82	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	46	0	0
T90	0	2	0	0
T110	0	59	0	0
T111	0	17	0	0
T112	0	48	0	0
T113	0	3	0	0
T130	0	20	0	0
T132	0	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1502	0	0
T24	251668	28	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	75	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	46	0	0
T90	0	8	0	0
T110	0	85	0	0
T111	0	24	0	0
T112	0	27	0	0
T113	0	15	0	0
T130	0	14	0	0
T131	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1608	0	0
T24	251668	20	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	102	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	49	0	0
T90	0	11	0	0
T110	0	72	0	0
T111	0	28	0	0
T112	0	47	0	0
T113	0	13	0	0
T130	0	21	0	0
T132	0	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1550	0	0
T24	251668	57	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	112	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	62	0	0
T90	0	9	0	0
T110	0	89	0	0
T111	0	8	0	0
T113	0	4	0	0
T120	0	1	0	0
T130	0	9	0	0
T132	0	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1613	0	0
T24	251668	57	0	0
T25	153588	0	0	0
T33	3663	0	0	0
T34	3264	0	0	0
T54	0	97	0	0
T74	145975	0	0	0
T75	144090	0	0	0
T76	248614	0	0	0
T77	519691	0	0	0
T78	626893	0	0	0
T79	467165	0	0	0
T81	0	27	0	0
T90	0	10	0	0
T110	0	109	0	0
T111	0	24	0	0
T112	0	37	0	0
T113	0	4	0	0
T130	0	6	0	0
T132	0	5	0	0