Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100560096	1			T1	230032		T2	15586		T3	224215
all_values[1]	100560096	1			T1	230032		T2	15586		T3	224215
all_values[2]	100560096	1			T1	230032		T2	15586		T3	224215

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

506759

1

T1

13

T2

358

T3

14

auto[1]

301173529

1

T1

690083

T2

46400

T3

672631

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300148086

1

T1

688389

T2

46332

T3

670875

auto[1]

1532202

1

T1

1707

T2

426

T3

1770

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	173249	1			T1	1		T3	3		T13	5
all_values[0]	auto[0]	auto[1]	2055	1			T1	2		T3	4		T13	2
all_values[0]	auto[1]	auto[0]	99876113	1			T1	229462		T2	15444		T3	223622
all_values[0]	auto[1]	auto[1]	508679	1			T1	567		T2	142		T3	586
all_values[1]	auto[0]	auto[0]	134650	1			T1	4		T2	178		T12	2
all_values[1]	auto[0]	auto[1]	1608	1			T1	3		T2	1		T12	1
all_values[1]	auto[1]	auto[0]	99914712	1			T1	229459		T2	15266		T3	223625
all_values[1]	auto[1]	auto[1]	509126	1			T1	566		T2	141		T3	590
all_values[2]	auto[0]	auto[0]	193629	1			T1	1		T2	178		T3	3
all_values[2]	auto[0]	auto[1]	1568	1			T1	2		T2	1		T3	4
all_values[2]	auto[1]	auto[0]	99855733	1			T1	229462		T2	15266		T3	223622
all_values[2]	auto[1]	auto[1]	509166	1			T1	567		T2	141		T3	586