Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total588510
Category 0588510


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total588510
Severity 0588510


Summary for Assertions
NUMBERPERCENT
Total Number588100.00
Uncovered71.19
Success58198.81
Failure00.00
Incomplete40.68
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Summary for Cover Properties
NUMBERPERCENT
Total Number5100.00
Uncovered00.00
Matches5100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_kmac_core.ProcessLatchedCleared_A 002147483647000
tb.dut.u_tlul_adapter_msgfifo.rvalidHighReqFifoEmpty 002147483647000
tb.dut.u_tlul_adapter_msgfifo.rvalidHighWhenRspFifoFull 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.DataKnown_A 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.DataKnown_A 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 002147483647000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertKnownO_A 002147483647214748364700
tb.dut.CmdSparse_M 002147483647127874300
tb.dut.EnMaskingKnown_A 002147483647214748364700
tb.dut.EntropyReadyLatched_A 00214748364733746900
tb.dut.EntrySizeRegSameToEntrySizePkg_A 001033103300
tb.dut.ErrProcessedLatched_A 00214748364750700
tb.dut.FifoEmpty_A 002147483647214748364700
tb.dut.FpvSecCmErrorCheckFsmCheck_A 0021474836479000
tb.dut.FpvSecCmKeccackFsmCheck_A 0021474836479000
tb.dut.FpvSecCmKeyIndexCountCheck_A 0021474836479000
tb.dut.FpvSecCmKmacAppFsmCheck_A 0021474836479000
tb.dut.FpvSecCmKmacCoreFsmCheck_A 0021474836479000
tb.dut.FpvSecCmKmacFsmCheck_A 0021474836479000
tb.dut.FpvSecCmRegWeOnehotCheck_A 0021474836479000
tb.dut.FpvSecCmRoundCountCheck_A 0021474836479000
tb.dut.FpvSecCmSHA3FsmCheck_A 0021474836479000
tb.dut.FpvSecCmSHA3padFsmCheck_A 0021474836479000
tb.dut.FpvSecCmSentMsgCountCheck_A 0021474836479000
tb.dut.KmacCmd_A 002147483647214748364700
tb.dut.KmacDone_A 002147483647214748364700
tb.dut.KmacErr_A 002147483647214748364700
tb.dut.KmacStKnown_A 002147483647214748364700
tb.dut.NumAlerts2_A 001033103300
tb.dut.NumEntriesRegSameToNumEntriesPkg_A 001033103300
tb.dut.PrefixRegSameToPrefixPkg_A 001033103300
tb.dut.SecretKeyDivideBy32_A 001033103300
tb.dut.Sha3AbsorbedPulse_A 00214748364734715600
tb.dut.TlOAReadyKnown_A 002147483647214748364700
tb.dut.TlODValidKnown_A 002147483647214748364700
tb.dut.intr_fifo_empty.IntrTKind_A 001033103300
tb.dut.intr_kmac_done.IntrTKind_A 001033103300
tb.dut.intr_kmac_err.IntrTKind_A 001033103300
tb.dut.kmac_csr_assert.TlulOOBAddrErr_A 00214748364746464800
tb.dut.kmac_csr_assert.entropy_period_rd_A 002147483647196000
tb.dut.kmac_csr_assert.intr_enable_rd_A 002147483647243700
tb.dut.kmac_csr_assert.prefix_0_rd_A 002147483647168100
tb.dut.kmac_csr_assert.prefix_10_rd_A 002147483647169200
tb.dut.kmac_csr_assert.prefix_1_rd_A 002147483647163700
tb.dut.kmac_csr_assert.prefix_2_rd_A 002147483647159400
tb.dut.kmac_csr_assert.prefix_3_rd_A 002147483647183700
tb.dut.kmac_csr_assert.prefix_4_rd_A 002147483647170100
tb.dut.kmac_csr_assert.prefix_5_rd_A 002147483647185900
tb.dut.kmac_csr_assert.prefix_6_rd_A 002147483647160600
tb.dut.kmac_csr_assert.prefix_7_rd_A 002147483647176400
tb.dut.kmac_csr_assert.prefix_8_rd_A 002147483647161500
tb.dut.kmac_csr_assert.prefix_9_rd_A 002147483647163000
tb.dut.sha3pad_assert_cov_if.ProcessToRun_A 00214748364734715600
tb.dut.sha3pad_assert_cov_if.RunThenComplete_M 002147483647307349500
tb.dut.tlul_assert_device.aKnown_A 00214748364747464919100
tb.dut.tlul_assert_device.aKnown_AKnownEnable 002147483647214748364700
tb.dut.tlul_assert_device.aReadyKnown_A 002147483647214748364700
tb.dut.tlul_assert_device.dKnown_A 00214748364789689981300
tb.dut.tlul_assert_device.dKnown_AKnownEnable 002147483647214748364700
tb.dut.tlul_assert_device.dReadyKnown_A 002147483647214748364700
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 00214748364723372185200
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 00214748364779329500
tb.dut.tlul_assert_device.gen_device.contigMask_M 00214748364734822915900
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00214748364746785765600
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 00214748364768354400
tb.dut.tlul_assert_device.gen_device.legalAParam_M 00214748364747464919100
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00214748364789689981300
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 00214748364747464919100
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00214748364789689981300
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00214748364789689981300
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00214748364789689981300
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 00214748364754668800
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 00214748364747958100
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 001248124800
tb.dut.u_app_intf.AppIntfInRange_A 001033103300
tb.dut.u_app_intf.SideloadKeySameToDigest_A 001033103300
tb.dut.u_app_intf.u_appid_arb.CheckHotOne_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.CheckNGreaterZero_A 001033103300
tb.dut.u_app_intf.u_appid_arb.GntImpliesReady_A 002147483647707300
tb.dut.u_app_intf.u_appid_arb.GntImpliesValid_A 002147483647707300
tb.dut.u_app_intf.u_appid_arb.GrantKnown_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.IdxKnown_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.IndexIsCorrect_A 002147483647707300
tb.dut.u_app_intf.u_appid_arb.NoReadyValidNoGrant_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.Priority_A 002147483647293556300
tb.dut.u_app_intf.u_appid_arb.ReadyAndValidImplyGrant_A 002147483647707300
tb.dut.u_app_intf.u_appid_arb.ReqAndReadyImplyGrant_A 002147483647707300
tb.dut.u_app_intf.u_appid_arb.ReqImpliesValid_A 002147483647293556300
tb.dut.u_app_intf.u_appid_arb.ValidKnown_A 002147483647214748364700
tb.dut.u_app_intf.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_app_intf.u_state_regs_A 002147483647214748364700
tb.dut.u_errchk.ExpectedModeStrengthBits_A 001033103300
tb.dut.u_errchk.ExpectedStSwCmdBits_A 001033103300
tb.dut.u_errchk.StKnown_A 002147483647214748364700
tb.dut.u_errchk.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_errchk.u_state_regs_A 002147483647214748364700
tb.dut.u_kmac_core.AckOnlyInMessageState_A 002147483647770219100
tb.dut.u_kmac_core.KeyDataStable_M 00214748364750727500
tb.dut.u_kmac_core.KeyLengthStable_M 00214748364728213900
tb.dut.u_kmac_core.KmacEnStable_M 0021474836472199000
tb.dut.u_kmac_core.MaxKeyLenMatchToKey512_A 001033103300
tb.dut.u_kmac_core.ModeStable_M 0021474836473357300
tb.dut.u_kmac_core.StrengthStable_M 0021474836474031400
tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer.ValidWidth_A 001033103300
tb.dut.u_kmac_core.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_kmac_core.u_state_regs_A 002147483647214748364700
tb.dut.u_msgfifo.FlushStInValid_A 002147483647214748364700
tb.dut.u_msgfifo.MessageValid_a 00214748364710878046100
tb.dut.u_msgfifo.PackerDoneDelay_A 002147483647214748364700
tb.dut.u_msgfifo.PackerDoneValid_a 00214748364734715600
tb.dut.u_msgfifo.u_msgfifo.DataKnown_A 0021474836476087295800
tb.dut.u_msgfifo.u_msgfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_msgfifo.u_msgfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_msgfifo.u_msgfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836476087295800
tb.dut.u_msgfifo.u_packer.DataIStable_M 00214748364712648501033
tb.dut.u_msgfifo.u_packer.DataOStableWhenPending_A 00214748364711162001033
tb.dut.u_msgfifo.u_packer.ExFlushValid_M 00214748364734715600
tb.dut.u_msgfifo.u_packer.ExcessiveDataStored_A 0021474836475448900
tb.dut.u_msgfifo.u_packer.ExcessiveMaskStored_A 0021474836475448900
tb.dut.u_msgfifo.u_packer.FlushFollowedByDone_A 00214748364734715601033
tb.dut.u_msgfifo.u_packer.ValidIDeassertedOnFlush_M 00214748364754752500
tb.dut.u_msgfifo.u_packer.ValidOAssertedForStoredDataGTEOutW_A 0021474836474756035200
tb.dut.u_msgfifo.u_packer.ValidOPairedWidthReadyI_A 00214748364711162000
tb.dut.u_msgfifo.u_packer.g_byte_assert.InputDividedBy8_A 001033103300
tb.dut.u_msgfifo.u_packer.g_byte_assert.OutputDividedBy8_A 001033103300
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A 00214748364710878046100
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A 0021474836474775920000
tb.dut.u_msgfifo.u_packer.gen_mask_assert.ContiguousOnesMask_M 00214748364710878046100
tb.dut.u_prim_lc_sync.NumCopiesMustBeGreaterZero_A 001033103300
tb.dut.u_prim_lc_sync.OutputsKnown_A 002147483647214748364700
tb.dut.u_prim_lc_sync.gen_flops.OutputDelay_A 002147483647214748364703099
tb.dut.u_reg.en2addrHit 00214748364730892273200
tb.dut.u_reg.reAfterRv 00214748364730892273200
tb.dut.u_reg.rePulse 00214748364720287459500
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_err_processed.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_err_processed.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_kmac_en.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_kmac_en.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_kstrength.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_kstrength.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_mode.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_mode.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_msg_mask.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_msg_mask.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_sideload.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_sideload.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_state_endianness.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_cfg_shadowed_state_endianness.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_chk.PayLoadWidthCheck 001248124800
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.CheckSwAccessIsLegal_A 001248124800
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_reg_if.AllowedLatency_A 001248124800
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 001248124800
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 001248124800
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001248124800
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001248124800
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 001248124800
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 001248124800
tb.dut.u_reg.u_socket.NotOverflowed_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A 00214748364747464919100
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A 00214748364789689981300
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 0021474836473804455500
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 0021474836477236038300
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00214748364711185690700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00214748364721344509000
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 00214748364731103490700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 00214748364761109434000
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001248124800
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 001248124800
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 001248124800
tb.dut.u_reg.u_socket.maxN 001248124800
tb.dut.u_reg.wePulse 00214748364710604813700
tb.dut.u_sha3.ErrDetection_A 002147483647790461100
tb.dut.u_sha3.FsmKnown_A 002147483647214748364700
tb.dut.u_sha3.KeccakIdleWhenNoRunHs_A 0021474836477739519100
tb.dut.u_sha3.MuxSelKnown_A 002147483647214748364700
tb.dut.u_sha3.SwRunInSqueezing_a 00214748364715130000
tb.dut.u_sha3.gen_chk_digest_unmasked.StateZeroInvalid_A 002147483647214748364700
tb.dut.u_sha3.u_keccak.ClearAssertStIdle_A 00214748364734713000
tb.dut.u_sha3.u_keccak.OneHot0ValidAndRun_A 002147483647214748364700
tb.dut.u_sha3.u_keccak.ValidRunAssertStIdle_A 0021474836475623246400
tb.dut.u_sha3.u_keccak.WidthDivisableByDInWidth_A 001033103300
tb.dut.u_sha3.u_keccak.gen_unmask_st_chk.UnmaskValidStates_A 002147483647214748364700
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidL_A 001033103300
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidRound_A 001033103300
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidW_A 001033103300
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidWidth_A 001033103300
tb.dut.u_sha3.u_keccak.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_sha3.u_keccak.u_state_regs_A 002147483647214748364700
tb.dut.u_sha3.u_pad.AbsorbedPulse_A 00214748364734715600
tb.dut.u_sha3.u_pad.AlwaysPartialMsgBuf_M 00214748364719820800
tb.dut.u_sha3.u_pad.CompleteBlockWhenProcess_A 00214748364733563600
tb.dut.u_sha3.u_pad.DoneCondition_M 00214748364734713000
tb.dut.u_sha3.u_pad.DonePulse_A 00214748364734713000
tb.dut.u_sha3.u_pad.KeccakAddrInRange_A 0021474836475300766100
tb.dut.u_sha3.u_pad.KeccakRunPulse_A 002147483647307350300
tb.dut.u_sha3.u_pad.MessageCondition_M 0021474836474829317300
tb.dut.u_sha3.u_pad.ModeStableDuringOp_M 0021474836473357300
tb.dut.u_sha3.u_pad.MsgReadyCondition_A 002147483647214748364700
tb.dut.u_sha3.u_pad.MsgWidthidth_A 001033103300
tb.dut.u_sha3.u_pad.NoPartialMsgFifo_M 0021474836474809496500
tb.dut.u_sha3.u_pad.Pad01NotAttheEndOfBlock_A 00214748364733638300
tb.dut.u_sha3.u_pad.PartialEndOfMsg_M 00214748364719820800
tb.dut.u_sha3.u_pad.PrefixLessThanBlock_A 001033103300
tb.dut.u_sha3.u_pad.ProcessCondition_M 00214748364734715600
tb.dut.u_sha3.u_pad.ProcessPulse_A 00214748364734715600
tb.dut.u_sha3.u_pad.StartCondition_M 00214748364734720500
tb.dut.u_sha3.u_pad.StartProcessDoneMutex_a 002147483647214748364700
tb.dut.u_sha3.u_pad.StartPulse_A 00214748364734720500
tb.dut.u_sha3.u_pad.StrengthStableDuringOp_M 0021474836474031400
tb.dut.u_sha3.u_pad.u_prefix_slicer.ValidWidth_A 001033103300
tb.dut.u_sha3.u_pad.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_sha3.u_pad.u_state_regs_A 002147483647214748364700
tb.dut.u_sha3.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_sha3.u_state_regs_A 002147483647214748364700
tb.dut.u_sha3_done_sender.OutputsKnown_A 002147483647214748364700
tb.dut.u_state_regs.AssertConnected_A 001033103300
tb.dut.u_state_regs_A 002147483647214748364700
tb.dut.u_staterd.gen_slicer[0].u_state_slice.ValidWidth_A 001033103300
tb.dut.u_staterd.u_tlul_adapter.AddrOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.DataIntgOptions_A 001033103300
tb.dut.u_staterd.u_tlul_adapter.ReqOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.SramDwHasByteGranularity_A 001033103300
tb.dut.u_staterd.u_tlul_adapter.SramDwIsMultipleOfTlulWidth_A 001033103300
tb.dut.u_staterd.u_tlul_adapter.TlOutKnownIfFifoKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.TlOutValidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.WdataOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.WeOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.WmaskOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.adapterNoReadOrWrite 001033103300
tb.dut.u_staterd.u_tlul_adapter.rvalidHighReqFifoEmpty 0021474836473667704500
tb.dut.u_staterd.u_tlul_adapter.rvalidHighWhenRspFifoFull 0021474836473667704500
tb.dut.u_staterd.u_tlul_adapter.u_err.dataWidthOnly32_A 001033103300
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.DataKnown_A 0021474836477235389000
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836477235389000
tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen.DataWidthCheck_A 001033103300
tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen.PayLoadWidthCheck 001033103300
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.DataKnown_A 0021474836477107178500
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836477107178500
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.DataKnown_A 0021474836473667704500
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836473667704500
tb.dut.u_tlul_adapter_msgfifo.AddrOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.DataIntgOptions_A 001033103300
tb.dut.u_tlul_adapter_msgfifo.ReqOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.SramDwHasByteGranularity_A 001033103300
tb.dut.u_tlul_adapter_msgfifo.SramDwIsMultipleOfTlulWidth_A 001033103300
tb.dut.u_tlul_adapter_msgfifo.TlOutKnownIfFifoKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.TlOutValidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.WdataOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.WeOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.WmaskOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.adapterNoReadOrWrite 001033103300
tb.dut.u_tlul_adapter_msgfifo.u_err.dataWidthOnly32_A 001033103300
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.DataKnown_A 00214748364721341433600
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00214748364721341433600
tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen.DataWidthCheck_A 001033103300
tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen.PayLoadWidthCheck 001033103300
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.WreadyKnown_A 002147483647214748364700

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_msgfifo.u_packer.DataIStable_M 00214748364712648501033
tb.dut.u_msgfifo.u_packer.DataOStableWhenPending_A 00214748364711162001033
tb.dut.u_msgfifo.u_packer.FlushFollowedByDone_A 00214748364734715601033
tb.dut.u_prim_lc_sync.gen_flops.OutputDelay_A 002147483647214748364703099


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021474836477041227041220
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021474836471011010
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021474836471011010
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00214748364787870
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00214748364747470
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00214748364767670
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00214748364754540
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002147483647934393430
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 002147483647877770587777050
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0021474836472576793512576793511218

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021474836477041227041220
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021474836471011010
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021474836471011010
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00214748364787870
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00214748364747470
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00214748364767670
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00214748364754540
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002147483647934393430
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 002147483647877770587777050
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0021474836472576793512576793511218


Detail Report for Cover Properties

Cover Properties Matches:
COVER PROPERTIESCATEGORYSEVERITYATTEMPTSMATCHESINCOMPLETESRC
tb.dut.u_app_intf.AppIntfUseDifferentSizeKey_C 00214748364727710
tb.dut.u_sha3.u_pad.StComplete_C 00214748364786789000
tb.dut.u_sha3.u_pad.StMessageFeed_C 00214748364721474836470
tb.dut.u_sha3.u_pad.StPadSendMsg_C 00214748364738568060
tb.dut.u_sha3.u_pad.StPad_C 0021474836473363830

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