Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335964 |
1 |
|
|
T1 |
2 |
|
T2 |
196 |
|
T3 |
780 |
auto[1] |
358096 |
1 |
|
|
T1 |
778 |
|
T13 |
286 |
|
T14 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174910 |
1 |
|
|
T1 |
194 |
|
T2 |
40 |
|
T3 |
196 |
lower_val |
171937 |
1 |
|
|
T1 |
204 |
|
T2 |
64 |
|
T3 |
201 |
zero_val |
1784 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346068 |
1 |
|
|
T1 |
408 |
|
T2 |
108 |
|
T3 |
412 |
lower_val |
347982 |
1 |
|
|
T1 |
372 |
|
T2 |
88 |
|
T3 |
368 |
zero_val |
10 |
1 |
|
|
T141 |
2 |
|
T142 |
2 |
|
T143 |
4 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42056 |
1 |
|
|
T2 |
26 |
|
T3 |
103 |
|
T12 |
50 |
higher_val |
higher_val |
auto[1] |
45148 |
1 |
|
|
T1 |
95 |
|
T13 |
48 |
|
T14 |
2 |
higher_val |
lower_val |
auto[0] |
42538 |
1 |
|
|
T1 |
1 |
|
T2 |
14 |
|
T3 |
93 |
higher_val |
lower_val |
auto[1] |
45164 |
1 |
|
|
T1 |
98 |
|
T13 |
34 |
|
T14 |
1 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T143 |
3 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T141 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
41572 |
1 |
|
|
T2 |
36 |
|
T3 |
107 |
|
T12 |
53 |
lower_val |
higher_val |
auto[1] |
44246 |
1 |
|
|
T1 |
109 |
|
T13 |
39 |
|
T14 |
1 |
lower_val |
lower_val |
auto[0] |
41523 |
1 |
|
|
T2 |
28 |
|
T3 |
94 |
|
T12 |
63 |
lower_val |
lower_val |
auto[1] |
44593 |
1 |
|
|
T1 |
95 |
|
T13 |
37 |
|
T14 |
1 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T142 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T141 |
1 |
|
T144 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
689 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
237 |
1 |
|
|
T13 |
2 |
|
T101 |
4 |
|
T102 |
1 |
zero_val |
lower_val |
auto[0] |
625 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
233 |
1 |
|
|
T13 |
1 |
|
T25 |
1 |
|
T101 |
4 |