Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100560096	1			T1	230032		T2	15586		T3	224215
all_pins[1]	100560096	1			T1	230032		T2	15586		T3	224215
all_pins[2]	100560096	1			T1	230032		T2	15586		T3	224215

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300896383	1			T1	689529		T2	46616		T3	672059
values[0x1]	783905	1			T1	567		T2	142		T3	586
transitions[0x0=>0x1]	782199	1			T1	567		T2	142		T3	586
transitions[0x1=>0x0]	782219	1			T1	567		T2	142		T3	586

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100051417	1			T1	229465		T2	15444		T3	223629
all_pins[0]	values[0x1]	508679	1			T1	567		T2	142		T3	586
all_pins[0]	transitions[0x0=>0x1]	508668	1			T1	567		T2	142		T3	586
all_pins[0]	transitions[0x1=>0x0]	64	1			T148	3		T149	3		T150	3
all_pins[1]	values[0x0]	100560021	1			T1	230032		T2	15586		T3	224215
all_pins[1]	values[0x1]	75	1			T148	3		T149	3		T150	3
all_pins[1]	transitions[0x0=>0x1]	58	1			T148	3		T149	3		T150	3
all_pins[1]	transitions[0x1=>0x0]	275134	1			T22	524		T31	1189		T25	2659
all_pins[2]	values[0x0]	100284945	1			T1	230032		T2	15586		T3	224215
all_pins[2]	values[0x1]	275151	1			T22	524		T31	1189		T25	2659
all_pins[2]	transitions[0x0=>0x1]	273473	1			T22	523		T31	1189		T25	2641
all_pins[2]	transitions[0x1=>0x0]	507021	1			T1	567		T2	142		T3	586