Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10719145 |
1 |
|
|
T1 |
2730 |
|
T2 |
15623 |
|
T3 |
2730 |
auto[1] |
25709418 |
1 |
|
|
T1 |
19500 |
|
T2 |
22326 |
|
T3 |
19500 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36309418 |
1 |
|
|
T1 |
22230 |
|
T2 |
37872 |
|
T3 |
22230 |
triple_byte_access |
39550 |
1 |
|
|
T2 |
25 |
|
T13 |
29 |
|
T15 |
29 |
halfword_access |
39948 |
1 |
|
|
T2 |
25 |
|
T13 |
38 |
|
T15 |
49 |
byte_access |
39647 |
1 |
|
|
T2 |
27 |
|
T13 |
40 |
|
T15 |
44 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10600000 |
1 |
|
|
T1 |
2730 |
|
T2 |
15546 |
|
T3 |
2730 |
auto[0] |
triple_byte_access |
39550 |
1 |
|
|
T2 |
25 |
|
T13 |
29 |
|
T15 |
29 |
auto[0] |
halfword_access |
39948 |
1 |
|
|
T2 |
25 |
|
T13 |
38 |
|
T15 |
49 |
auto[0] |
byte_access |
39647 |
1 |
|
|
T2 |
27 |
|
T13 |
40 |
|
T15 |
44 |
auto[1] |
word_access |
25709418 |
1 |
|
|
T1 |
19500 |
|
T2 |
22326 |
|
T3 |
19500 |