Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258884586

1

T1

61983

T2

145729

T3

66323

full_word

201289354

1

T1

329285

T2

100041

T3

113337

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	460173660	1			T1	391268		T2	245770		T3	179660
auto[TlIntgErrCmd]	90	1			T112	2		T113	2		T114	4
auto[TlIntgErrData]	103	1			T112	4		T113	4		T114	3
auto[TlIntgErrBoth]	87	1			T112	4		T113	4		T114	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241755243

1

T1

135319

T2

129079

T3

121153

auto[1]

218418697

1

T1

255949

T2

116690

T3

58507

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153781611	1			T1	58293		T2	859449		T3	39954
auto[TlIntgErrNone]	partial	auto[1]	105102715	1			T1	3690		T2	597841		T3	26369
auto[TlIntgErrNone]	full_word	auto[0]	87973506	1			T1	77026		T2	431347		T3	81199
auto[TlIntgErrNone]	full_word	auto[1]	113315828	1			T1	252259		T2	569067		T3	32138
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T113	1		T146	2		T172	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T112	2		T114	4		T146	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T113	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T146	1		T172	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T112	1		T113	2		T114	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T112	3		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T113	1		T174	1		T175	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T175	1		T178	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T112	1		T113	4		T114	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T112	3		T114	2		T172	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T146	1		T174	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T174	1		T176	1		T180	1