Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_sideload

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.66 100.00 94.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.87 100.00 99.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT93,T94,T95
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT94,T95,T96
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT94,T95,T96

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT93,T94,T95

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 16224 16224 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 16224 16224 0 0
T1 13 13 0 0
T2 13 13 0 0
T3 13 13 0 0
T12 13 13 0 0
T13 13 13 0 0
T14 13 13 0 0
T15 13 13 0 0
T16 13 13 0 0
T17 13 13 0 0
T18 13 13 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 10479755 10478780 0 0
T2 3385018 3385005 0 0
T3 2424448 2424370 0 0
T12 8022729 8022625 0 0
T13 2320292 2320201 0 0
T14 2449746 2449616 0 0
T15 1381913 1381900 0 0
T16 2253602 2253511 0 0
T17 2525549 2525458 0 0
T18 7698561 7698457 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T96,T97
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT96,T98,T99
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T3,T15
11CoveredT96,T98,T99

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T97

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T96,T100
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT96,T97,T98
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T12
10CoveredT1,T3,T12
11CoveredT96,T97,T98

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T100

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T96,T100
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT97,T101,T102
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT97,T101,T102

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T100

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T97,T101
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT98,T99,T103
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT98,T99,T103

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T97,T101

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T100,T97
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT96,T97,T101
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT96,T97,T101

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T100,T97

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T97,T101
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT96,T100,T97
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T16,T17

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T16,T17

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT3,T16,T17
10CoveredT3,T16,T17
11CoveredT96,T100,T97

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T97,T101

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T3,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T96,T100
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT95,T96,T97
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT95,T96,T97

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T100

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T97,T104
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT95,T96,T97
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT95,T96,T97

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T97,T104

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T100,T97
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT96,T97,T99
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT96,T97,T99

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T100,T97

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T100,T101
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT96,T97,T101
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT96,T97,T101

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T100,T101

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT95,T96,T100
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT100,T101,T99
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T21

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T21

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT19,T20,T21
10CoveredT19,T20,T21
11CoveredT100,T101,T99

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T100

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T19,T20,T21
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT97,T101,T105
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT95,T96,T97
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT95,T96,T97

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT97,T101,T105

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

Line Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT93,T94,T100
10CoveredT49,T56,T57

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT94,T100,T106
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T31,T27

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T31,T27

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT17,T31,T27
10CoveredT17,T31,T27
11CoveredT94,T100,T106

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT93,T94,T100

Branch Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T17,T31,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T49,T56,T57
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1248 1248 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1248 1248 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 806135 806060 0 0
T2 260386 260385 0 0
T3 186496 186490 0 0
T12 617133 617125 0 0
T13 178484 178477 0 0
T14 188442 188432 0 0
T15 106301 106300 0 0
T16 173354 173347 0 0
T17 194273 194266 0 0
T18 592197 592189 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%