Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
200909698 |
0 |
0 |
T1 |
806135 |
243371 |
0 |
0 |
T2 |
260386 |
255868 |
0 |
0 |
T3 |
186496 |
115103 |
0 |
0 |
T12 |
617133 |
212115 |
0 |
0 |
T13 |
178484 |
211353 |
0 |
0 |
T14 |
188442 |
223196 |
0 |
0 |
T15 |
106301 |
115690 |
0 |
0 |
T16 |
173354 |
92156 |
0 |
0 |
T17 |
194273 |
86413 |
0 |
0 |
T18 |
592197 |
482266 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
200909698 |
0 |
0 |
T1 |
806135 |
243371 |
0 |
0 |
T2 |
260386 |
255868 |
0 |
0 |
T3 |
186496 |
115103 |
0 |
0 |
T12 |
617133 |
212115 |
0 |
0 |
T13 |
178484 |
211353 |
0 |
0 |
T14 |
188442 |
223196 |
0 |
0 |
T15 |
106301 |
115690 |
0 |
0 |
T16 |
173354 |
92156 |
0 |
0 |
T17 |
194273 |
86413 |
0 |
0 |
T18 |
592197 |
482266 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 11 | 78.57 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 0 | 0 | |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
|
unreachable |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 13 | 5 | 38.46 |
Logical | 13 | 5 | 38.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 13 | 12 | 92.31 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
|
unreachable |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
|
unreachable |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Total | Covered | Percent |
Conditions | 17 | 8 | 47.06 |
Logical | 17 | 8 | 47.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Unreachable | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
6 |
85.71 |
TERNARY |
130 |
1 |
1 |
100.00 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Total | Covered | Percent |
Conditions | 24 | 21 | 87.50 |
Logical | 24 | 21 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T22,T32 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T22,T32,T29 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T13,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
62061808 |
0 |
0 |
T1 |
806135 |
280011 |
0 |
0 |
T2 |
260386 |
241576 |
0 |
0 |
T3 |
186496 |
10741 |
0 |
0 |
T12 |
617133 |
90678 |
0 |
0 |
T13 |
178484 |
135701 |
0 |
0 |
T14 |
188442 |
141753 |
0 |
0 |
T15 |
106301 |
108169 |
0 |
0 |
T16 |
173354 |
16681 |
0 |
0 |
T17 |
194273 |
13337 |
0 |
0 |
T18 |
592197 |
69082 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
62061808 |
0 |
0 |
T1 |
806135 |
280011 |
0 |
0 |
T2 |
260386 |
241576 |
0 |
0 |
T3 |
186496 |
10741 |
0 |
0 |
T12 |
617133 |
90678 |
0 |
0 |
T13 |
178484 |
135701 |
0 |
0 |
T14 |
188442 |
141753 |
0 |
0 |
T15 |
106301 |
108169 |
0 |
0 |
T16 |
173354 |
16681 |
0 |
0 |
T17 |
194273 |
13337 |
0 |
0 |
T18 |
592197 |
69082 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71086910 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
648103 |
0 |
0 |
T3 |
186496 |
306758 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
285089 |
0 |
0 |
T16 |
173354 |
281596 |
0 |
0 |
T17 |
194273 |
242378 |
0 |
0 |
T18 |
592197 |
59801 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71086910 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
648103 |
0 |
0 |
T3 |
186496 |
306758 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
285089 |
0 |
0 |
T16 |
173354 |
281596 |
0 |
0 |
T17 |
194273 |
242378 |
0 |
0 |
T18 |
592197 |
59801 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
37068479 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
144085 |
0 |
0 |
T3 |
186496 |
68093 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
63127 |
0 |
0 |
T16 |
173354 |
62597 |
0 |
0 |
T17 |
194273 |
54212 |
0 |
0 |
T18 |
592197 |
19220 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
37068479 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
144085 |
0 |
0 |
T3 |
186496 |
68093 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
63127 |
0 |
0 |
T16 |
173354 |
62597 |
0 |
0 |
T17 |
194273 |
54212 |
0 |
0 |
T18 |
592197 |
19220 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T15 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T15 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69780403 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
648103 |
0 |
0 |
T3 |
186496 |
306758 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
285089 |
0 |
0 |
T16 |
173354 |
281596 |
0 |
0 |
T17 |
194273 |
242378 |
0 |
0 |
T18 |
592197 |
59801 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69780403 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
648103 |
0 |
0 |
T3 |
186496 |
306758 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
285089 |
0 |
0 |
T16 |
173354 |
281596 |
0 |
0 |
T17 |
194273 |
242378 |
0 |
0 |
T18 |
592197 |
59801 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
481219112 |
0 |
0 |
T1 |
806135 |
519981 |
0 |
0 |
T2 |
260386 |
245770 |
0 |
0 |
T3 |
186496 |
207180 |
0 |
0 |
T12 |
617133 |
876379 |
0 |
0 |
T13 |
178484 |
873341 |
0 |
0 |
T14 |
188442 |
921496 |
0 |
0 |
T15 |
106301 |
138676 |
0 |
0 |
T16 |
173354 |
181957 |
0 |
0 |
T17 |
194273 |
161665 |
0 |
0 |
T18 |
592197 |
646902 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
847734177 |
0 |
0 |
T1 |
806135 |
391268 |
0 |
0 |
T2 |
260386 |
110574 |
0 |
0 |
T3 |
186496 |
817336 |
0 |
0 |
T12 |
617133 |
876379 |
0 |
0 |
T13 |
178484 |
873341 |
0 |
0 |
T14 |
188442 |
921496 |
0 |
0 |
T15 |
106301 |
487500 |
0 |
0 |
T16 |
173354 |
688008 |
0 |
0 |
T17 |
194273 |
624526 |
0 |
0 |
T18 |
592197 |
200598 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
39395802 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
144085 |
0 |
0 |
T3 |
186496 |
68093 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
63127 |
0 |
0 |
T16 |
173354 |
62597 |
0 |
0 |
T17 |
194273 |
54212 |
0 |
0 |
T18 |
592197 |
19220 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71095392 |
0 |
0 |
T1 |
806135 |
75038 |
0 |
0 |
T2 |
260386 |
648103 |
0 |
0 |
T3 |
186496 |
306758 |
0 |
0 |
T12 |
617133 |
21692 |
0 |
0 |
T13 |
178484 |
21692 |
0 |
0 |
T14 |
188442 |
22230 |
0 |
0 |
T15 |
106301 |
285089 |
0 |
0 |
T16 |
173354 |
281596 |
0 |
0 |
T17 |
194273 |
242378 |
0 |
0 |
T18 |
592197 |
59801 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
113132852 |
0 |
0 |
T1 |
806135 |
358698 |
0 |
0 |
T2 |
260386 |
568681 |
0 |
0 |
T3 |
186496 |
24677 |
0 |
0 |
T12 |
617133 |
212115 |
0 |
0 |
T13 |
178484 |
211353 |
0 |
0 |
T14 |
188442 |
223196 |
0 |
0 |
T15 |
106301 |
246391 |
0 |
0 |
T16 |
173354 |
19373 |
0 |
0 |
T17 |
194273 |
18467 |
0 |
0 |
T18 |
592197 |
155632 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
200937706 |
0 |
0 |
T1 |
806135 |
243371 |
0 |
0 |
T2 |
260386 |
255868 |
0 |
0 |
T3 |
186496 |
115103 |
0 |
0 |
T12 |
617133 |
212115 |
0 |
0 |
T13 |
178484 |
211353 |
0 |
0 |
T14 |
188442 |
223196 |
0 |
0 |
T15 |
106301 |
115690 |
0 |
0 |
T16 |
173354 |
92156 |
0 |
0 |
T17 |
194273 |
86413 |
0 |
0 |
T18 |
592197 |
482266 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
313975707 |
0 |
0 |
T1 |
806135 |
72859 |
0 |
0 |
T2 |
260386 |
174493 |
0 |
0 |
T3 |
186496 |
86890 |
0 |
0 |
T12 |
617133 |
642572 |
0 |
0 |
T13 |
178484 |
640296 |
0 |
0 |
T14 |
188442 |
676070 |
0 |
0 |
T15 |
106301 |
751562 |
0 |
0 |
T16 |
173354 |
68590 |
0 |
0 |
T17 |
194273 |
64729 |
0 |
0 |
T18 |
592197 |
472050 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
806135 |
806060 |
0 |
0 |
T2 |
260386 |
260385 |
0 |
0 |
T3 |
186496 |
186490 |
0 |
0 |
T12 |
617133 |
617125 |
0 |
0 |
T13 |
178484 |
178477 |
0 |
0 |
T14 |
188442 |
188432 |
0 |
0 |
T15 |
106301 |
106300 |
0 |
0 |
T16 |
173354 |
173347 |
0 |
0 |
T17 |
194273 |
194266 |
0 |
0 |
T18 |
592197 |
592189 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1248 |
1248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |