Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256602869	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

201779381

1

T1

887303

T2

887731

T3

358691

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	242298673	1			T1	110441		T2	111357		T3	470063
values[0x0]	103801926	1			T1	447876		T2	451558		T3	215667
values[0x1]	112281651	1			T1	485360		T2	490733		T3	235525

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199996099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

258386151

1

T1

113966

T2

114508

T3

482302

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1368911	1			T1	7956		T2	8172		T3	3669
valid_sources[0x01]	1887708	1			T1	7915		T2	8068		T3	3607
valid_sources[0x02]	2022819	1			T1	7875		T2	8315		T3	3611
valid_sources[0x03]	1369392	1			T1	8034		T2	8143		T3	3651
valid_sources[0x04]	1368567	1			T1	7852		T2	7996		T3	3602
valid_sources[0x05]	1374818	1			T1	8075		T2	7992		T3	3635
valid_sources[0x06]	1372972	1			T1	7946		T2	8285		T3	3707
valid_sources[0x07]	1365606	1			T1	8075		T2	8181		T3	3564
valid_sources[0x08]	2030231	1			T1	7893		T2	7804		T3	3510
valid_sources[0x09]	1373890	1			T1	8161		T2	8209		T3	3541
valid_sources[0x0a]	1508175	1			T1	7957		T2	7672		T3	3738
valid_sources[0x0b]	1378483	1			T1	7891		T2	8506		T3	3660
valid_sources[0x0c]	1364889	1			T1	7902		T2	7772		T3	3518
valid_sources[0x0d]	2270224	1			T1	7943		T2	7896		T3	3526
valid_sources[0x0e]	1373118	1			T1	7978		T2	7997		T3	3588
valid_sources[0x0f]	3779384	1			T1	7957		T2	8002		T3	3504
valid_sources[0x10]	1368643	1			T1	7928		T2	7489		T3	3534
valid_sources[0x11]	3479352	1			T1	7907		T2	8368		T3	3628
valid_sources[0x12]	1368542	1			T1	8008		T2	7978		T3	3663
valid_sources[0x13]	1915808	1			T1	8016		T2	7990		T3	3606
valid_sources[0x14]	1389915	1			T1	7849		T2	7809		T3	3550
valid_sources[0x15]	1493016	1			T1	8001		T2	8154		T3	3745
valid_sources[0x16]	1368184	1			T1	7962		T2	7988		T3	3591
valid_sources[0x17]	1404537	1			T1	7913		T2	7876		T3	3610
valid_sources[0x18]	1831895	1			T1	8024		T2	7910		T3	3501
valid_sources[0x19]	1370659	1			T1	7807		T2	8169		T3	3689
valid_sources[0x1a]	3187713	1			T1	8027		T2	8078		T3	3539
valid_sources[0x1b]	1370435	1			T1	7880		T2	8088		T3	3561
valid_sources[0x1c]	1395034	1			T1	7930		T2	8098		T3	3482
valid_sources[0x1d]	1369707	1			T1	7910		T2	8092		T3	3541
valid_sources[0x1e]	1372785	1			T1	7993		T2	8062		T3	3662
valid_sources[0x1f]	1365551	1			T1	7817		T2	8781		T3	3642
valid_sources[0x20]	1363512	1			T1	7948		T2	7949		T3	3528
valid_sources[0x21]	1474247	1			T1	7930		T2	7774		T3	3656
valid_sources[0x22]	1369917	1			T1	7878		T2	8203		T3	3645
valid_sources[0x23]	1402917	1			T1	7806		T2	7772		T3	3627
valid_sources[0x24]	2298391	1			T1	7966		T2	8086		T3	3567
valid_sources[0x25]	1368402	1			T1	7851		T2	8032		T3	3581
valid_sources[0x26]	1589720	1			T1	7980		T2	8402		T3	3745
valid_sources[0x27]	1506622	1			T1	8071		T2	8219		T3	3646
valid_sources[0x28]	1367163	1			T1	7932		T2	8073		T3	3667
valid_sources[0x29]	1436764	1			T1	7916		T2	8217		T3	3680
valid_sources[0x2a]	1399587	1			T1	7864		T2	8154		T3	3686
valid_sources[0x2b]	1534717	1			T1	7924		T2	8003		T3	3608
valid_sources[0x2c]	1368778	1			T1	7887		T2	7942		T3	3441
valid_sources[0x2d]	2298496	1			T1	8006		T2	7853		T3	3614
valid_sources[0x2e]	1409283	1			T1	7964		T2	8038		T3	3484
valid_sources[0x2f]	1370287	1			T1	7898		T2	8256		T3	3575
valid_sources[0x30]	1370382	1			T1	8000		T2	8018		T3	3597
valid_sources[0x31]	3431820	1			T1	7947		T2	8007		T3	3615
valid_sources[0x32]	1368990	1			T1	7991		T2	7884		T3	3626
valid_sources[0x33]	1367211	1			T1	7821		T2	8038		T3	3631
valid_sources[0x34]	1368473	1			T1	7997		T2	7877		T3	3649
valid_sources[0x35]	1368967	1			T1	8007		T2	8094		T3	3651
valid_sources[0x36]	1372811	1			T1	7826		T2	8135		T3	3649
valid_sources[0x37]	1374379	1			T1	7946		T2	7486		T3	3436
valid_sources[0x38]	3422494	1			T1	7894		T2	8203		T3	3570
valid_sources[0x39]	1389424	1			T1	7934		T2	8178		T3	3657
valid_sources[0x3a]	3805929	1			T1	7865		T2	7558		T3	3693
valid_sources[0x3b]	4849222	1			T1	7904		T2	8345		T3	3729
valid_sources[0x3c]	1367786	1			T1	8256		T2	7843		T3	3502
valid_sources[0x3d]	1413588	1			T1	7965		T2	7917		T3	3633
valid_sources[0x3e]	1373218	1			T1	8022		T2	8397		T3	3595
valid_sources[0x3f]	1370830	1			T1	7908		T2	8120		T3	3600
valid_sources[0x40]	1375479	1			T1	7894		T2	7623		T3	3615
valid_sources[0x41]	1362040	1			T1	8157		T2	8047		T3	3645
valid_sources[0x42]	3777219	1			T1	7968		T2	7704		T3	3620
valid_sources[0x43]	1543889	1			T1	7717		T2	8333		T3	3531
valid_sources[0x44]	1370100	1			T1	8063		T2	7763		T3	3565
valid_sources[0x45]	1391116	1			T1	8051		T2	8401		T3	3563
valid_sources[0x46]	1492651	1			T1	7986		T2	8076		T3	3660
valid_sources[0x47]	1418576	1			T1	7924		T2	7836		T3	3643
valid_sources[0x48]	1372923	1			T1	7894		T2	7693		T3	3593
valid_sources[0x49]	1365550	1			T1	7984		T2	7856		T3	3560
valid_sources[0x4a]	1803081	1			T1	7904		T2	8274		T3	3473
valid_sources[0x4b]	1367009	1			T1	7946		T2	7766		T3	3521
valid_sources[0x4c]	1874460	1			T1	8053		T2	8047		T3	3669
valid_sources[0x4d]	1370091	1			T1	7907		T2	7624		T3	3629
valid_sources[0x4e]	1406686	1			T1	8086		T2	7913		T3	3562
valid_sources[0x4f]	1505356	1			T1	7975		T2	8199		T3	3485
valid_sources[0x50]	3916788	1			T1	7956		T2	8013		T3	3438
valid_sources[0x51]	1422200	1			T1	7991		T2	7753		T3	3615
valid_sources[0x52]	1377181	1			T1	8059		T2	7664		T3	3514
valid_sources[0x53]	5158237	1			T1	7908		T2	8205		T3	3528
valid_sources[0x54]	3877665	1			T1	7949		T2	7872		T3	3667
valid_sources[0x55]	1365778	1			T1	7982		T2	8000		T3	3696
valid_sources[0x56]	1370471	1			T1	7873		T2	8209		T3	3619
valid_sources[0x57]	1437314	1			T1	8091		T2	8014		T3	3666
valid_sources[0x58]	1360826	1			T1	7926		T2	8082		T3	3607
valid_sources[0x59]	1365540	1			T1	7988		T2	8902		T3	3688
valid_sources[0x5a]	1424255	1			T1	8083		T2	8138		T3	3663
valid_sources[0x5b]	1370447	1			T1	8038		T2	8175		T3	3617
valid_sources[0x5c]	1367966	1			T1	7932		T2	8017		T3	3655
valid_sources[0x5d]	2272224	1			T1	7875		T2	8103		T3	3618
valid_sources[0x5e]	1365361	1			T1	8067		T2	8156		T3	3550
valid_sources[0x5f]	2302148	1			T1	7852		T2	7822		T3	3640
valid_sources[0x60]	1891703	1			T1	8151		T2	8287		T3	3630
valid_sources[0x61]	1377706	1			T1	7918		T2	8124		T3	3524
valid_sources[0x62]	1370734	1			T1	7933		T2	7777		T3	3469
valid_sources[0x63]	1371615	1			T1	7946		T2	7915		T3	3635
valid_sources[0x64]	1367326	1			T1	8147		T2	7970		T3	3638
valid_sources[0x65]	1370314	1			T1	8005		T2	7977		T3	3574
valid_sources[0x66]	1365257	1			T1	7845		T2	7969		T3	3562
valid_sources[0x67]	1369832	1			T1	8095		T2	7772		T3	3606
valid_sources[0x68]	1364097	1			T1	7974		T2	8444		T3	3611
valid_sources[0x69]	1682402	1			T1	8027		T2	8090		T3	3670
valid_sources[0x6a]	3449028	1			T1	7893		T2	7760		T3	3484
valid_sources[0x6b]	1587301	1			T1	7895		T2	8658		T3	3668
valid_sources[0x6c]	2321473	1			T1	8084		T2	8532		T3	3538
valid_sources[0x6d]	1923460	1			T1	7897		T2	7704		T3	3589
valid_sources[0x6e]	2245303	1			T1	7916		T2	8034		T3	3563
valid_sources[0x6f]	1376927	1			T1	7875		T2	8045		T3	3524
valid_sources[0x70]	1360990	1			T1	8041		T2	7847		T3	3657
valid_sources[0x71]	2299310	1			T1	7924		T2	8098		T3	3646
valid_sources[0x72]	2312587	1			T1	7796		T2	7936		T3	3531
valid_sources[0x73]	2377371	1			T1	7694		T2	7867		T3	3654
valid_sources[0x74]	1365428	1			T1	7716		T2	8234		T3	3515
valid_sources[0x75]	1400481	1			T1	7974		T2	7877		T3	3730
valid_sources[0x76]	3756100	1			T1	8020		T2	7932		T3	3617
valid_sources[0x77]	1370713	1			T1	8011		T2	7941		T3	3641
valid_sources[0x78]	1369253	1			T1	8012		T2	8429		T3	3668
valid_sources[0x79]	3813421	1			T1	7920		T2	7732		T3	3745
valid_sources[0x7a]	1370934	1			T1	8044		T2	7924		T3	3584
valid_sources[0x7b]	1369507	1			T1	8124		T2	7840		T3	3576
valid_sources[0x7c]	1368728	1			T1	8007		T2	7883		T3	3629
valid_sources[0x7d]	2034207	1			T1	7957		T2	8166		T3	3498
valid_sources[0x7e]	1516929	1			T1	8060		T2	8526		T3	3622
valid_sources[0x7f]	1451718	1			T1	7944		T2	7929		T3	3616
valid_sources[0x80]	2060962	1			T1	8004		T2	7926		T3	3636

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88384143

1

T1

418273

T2

421153

T3

134538

values[0x0]

all_enables

biggest_size

61024712

1

T1

254090

T2

253248

T3

121164

values[0x1]

all_enables

biggest_size

52370526

1

T1

214940

T2

213330

T3

102989