Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258651129

1

T1

115034

T2

116813

T3

562564

full_word

201908089

1

T1

887303

T2

887731

T3

358691

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	460558918	1			T1	203764		T2	205586		T3	921255
auto[TlIntgErrCmd]	90	1			T114	5		T115	9		T116	2
auto[TlIntgErrData]	112	1			T114	10		T115	6		T116	9
auto[TlIntgErrBoth]	98	1			T114	5		T115	5		T116	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242697770

1

T1

110441

T2

111357

T3

470063

auto[1]

217861448

1

T1

933236

T2

942291

T3

451192

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154281155	1			T1	686137		T2	692417		T3	335525
auto[TlIntgErrNone]	partial	auto[1]	104369698	1			T1	464206		T2	475713		T3	227039
auto[TlIntgErrNone]	full_word	auto[0]	88416482	1			T1	418273		T2	421153		T3	134538
auto[TlIntgErrNone]	full_word	auto[1]	113491583	1			T1	469030		T2	466578		T3	224153
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T114	1		T115	3		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T114	4		T115	6		T116	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T166	1		T167	1		T168	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T165	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1			T114	5		T115	1		T116	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T114	4		T115	4		T116	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T114	1		T115	1		T166	3
auto[TlIntgErrData]	full_word	auto[1]	1	1			T169	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T114	3		T115	3		T116	4
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T114	1		T115	2		T116	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T114	1		T165	2		T170	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T169	1		T171	3		T172	1