Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256201734

1

T1

656

T2

949

T3

9868

full_word

199917859

1

T1

1421

T2

5236

T3

14358

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456119283	1			T1	2077		T2	6185		T3	24226
auto[TlIntgErrCmd]	102	1			T115	9		T116	4		T117	7
auto[TlIntgErrData]	100	1			T115	4		T116	3		T117	9
auto[TlIntgErrBoth]	108	1			T115	7		T116	3		T117	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239652102

1

T1

1081

T2

4112

T3

15440

auto[1]

216467491

1

T1

996

T2

2073

T3

8786

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152518288	1			T1	380		T2	527		T3	5990
auto[TlIntgErrNone]	partial	auto[1]	103683157	1			T1	276		T2	422		T3	3878
auto[TlIntgErrNone]	full_word	auto[0]	87133675	1			T1	701		T2	3585		T3	9450
auto[TlIntgErrNone]	full_word	auto[1]	112784163	1			T1	720		T2	1651		T3	4908
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T115	3		T116	1		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T115	6		T116	2		T117	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T116	1		T178	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T174	1		T180	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T115	3		T116	1		T117	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T115	1		T116	2		T117	7
auto[TlIntgErrData]	full_word	auto[0]	1	1			T179	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T181	1		T182	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T115	4		T116	2		T117	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T115	3		T116	1		T117	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T176	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T181	2		T174	1		T176	1