Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	580605	0	0
entropy_period_rd_A	2147483647	3006	0	0
intr_enable_rd_A	2147483647	3672	0	0
prefix_0_rd_A	2147483647	2987	0	0
prefix_10_rd_A	2147483647	3090	0	0
prefix_1_rd_A	2147483647	2929	0	0
prefix_2_rd_A	2147483647	3045	0	0
prefix_3_rd_A	2147483647	3058	0	0
prefix_4_rd_A	2147483647	3054	0	0
prefix_5_rd_A	2147483647	3161	0	0
prefix_6_rd_A	2147483647	3125	0	0
prefix_7_rd_A	2147483647	3145	0	0
prefix_8_rd_A	2147483647	3185	0	0
prefix_9_rd_A	2147483647	3192	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	580605	0	0
T19	442342	23404	0	0
T22	9056	0	0	0
T25	313440	0	0	0
T29	258602	0	0	0
T36	101078	0	0	0
T37	101174	0	0	0
T38	134304	0	0	0
T39	633333	0	0	0
T55	0	45041	0	0
T56	0	71283	0	0
T57	11013	0	0	0
T71	188618	0	0	0
T121	0	111219	0	0
T122	0	17504	0	0
T123	0	40845	0	0
T124	0	21285	0	0
T125	0	109465	0	0
T126	0	26090	0	0
T127	0	39507	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3006	0	0
T56	909040	257	0	0
T92	0	28	0	0
T107	0	10	0	0
T116	0	77	0	0
T117	0	70	0	0
T140	0	23	0	0
T141	0	6	0	0
T142	0	16	0	0
T143	0	3	0	0
T144	0	9	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3672	0	0
T56	909040	205	0	0
T92	0	35	0	0
T107	0	13	0	0
T116	0	84	0	0
T119	0	1	0	0
T140	0	25	0	0
T141	0	8	0	0
T142	0	22	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0
T154	0	21	0	0
T155	0	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2987	0	0
T56	909040	184	0	0
T92	0	20	0	0
T107	0	13	0	0
T116	0	31	0	0
T117	0	54	0	0
T140	0	21	0	0
T141	0	6	0	0
T142	0	27	0	0
T143	0	12	0	0
T144	0	2	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3090	0	0
T56	909040	176	0	0
T92	0	28	0	0
T107	0	3	0	0
T116	0	40	0	0
T117	0	58	0	0
T140	0	19	0	0
T141	0	6	0	0
T142	0	32	0	0
T143	0	22	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0
T156	0	14	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2929	0	0
T56	909040	199	0	0
T92	0	20	0	0
T107	0	18	0	0
T116	0	38	0	0
T117	0	48	0	0
T140	0	17	0	0
T141	0	5	0	0
T142	0	16	0	0
T143	0	4	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0
T156	0	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3045	0	0
T56	909040	121	0	0
T92	0	22	0	0
T107	0	29	0	0
T116	0	38	0	0
T117	0	48	0	0
T140	0	25	0	0
T141	0	10	0	0
T142	0	6	0	0
T143	0	10	0	0
T144	0	6	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3058	0	0
T56	909040	160	0	0
T92	0	16	0	0
T107	0	30	0	0
T116	0	41	0	0
T117	0	45	0	0
T140	0	27	0	0
T141	0	3	0	0
T142	0	28	0	0
T143	0	4	0	0
T144	0	7	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3054	0	0
T56	909040	172	0	0
T92	0	25	0	0
T107	0	11	0	0
T116	0	28	0	0
T117	0	27	0	0
T140	0	18	0	0
T141	0	10	0	0
T142	0	28	0	0
T143	0	15	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0
T156	0	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3161	0	0
T56	909040	205	0	0
T92	0	29	0	0
T107	0	14	0	0
T116	0	27	0	0
T117	0	27	0	0
T140	0	10	0	0
T141	0	8	0	0
T142	0	28	0	0
T143	0	14	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0
T156	0	12	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3125	0	0
T56	909040	139	0	0
T92	0	18	0	0
T107	0	7	0	0
T116	0	36	0	0
T117	0	40	0	0
T140	0	16	0	0
T141	0	9	0	0
T142	0	40	0	0
T143	0	24	0	0
T144	0	6	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3145	0	0
T56	909040	221	0	0
T92	0	36	0	0
T107	0	22	0	0
T116	0	48	0	0
T117	0	51	0	0
T140	0	19	0	0
T141	0	5	0	0
T142	0	8	0	0
T143	0	5	0	0
T144	0	1	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3185	0	0
T56	909040	213	0	0
T92	0	19	0	0
T107	0	11	0	0
T116	0	37	0	0
T117	0	39	0	0
T140	0	7	0	0
T141	0	5	0	0
T142	0	62	0	0
T143	0	17	0	0
T144	0	5	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3192	0	0
T56	909040	190	0	0
T92	0	34	0	0
T107	0	28	0	0
T116	0	33	0	0
T117	0	36	0	0
T140	0	17	0	0
T141	0	9	0	0
T142	0	24	0	0
T144	0	7	0	0
T145	124641	0	0	0
T146	216190	0	0	0
T147	6695	0	0	0
T148	41745	0	0	0
T149	765271	0	0	0
T150	574158	0	0	0
T151	171540	0	0	0
T152	206692	0	0	0
T153	98475	0	0	0
T156	0	10	0	0