Module Definition
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Module : kmac_errchk
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.06 96.72 96.67 90.91 96.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_errchk 97.88 96.72 96.67 100.00 96.00 100.00



Module Instance : tb.dut.u_errchk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.88 96.72 96.67 100.00 96.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.99 97.14 96.67 100.00 96.15 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : kmac_errchk
Line No.TotalCoveredPercent
TOTAL615996.72
ALWAYS185151386.67
CONT_ASSIGN23411100.00
ALWAYS24244100.00
ALWAYS24844100.00
ALWAYS26444100.00
CONT_ASSIGN30200
ALWAYS30766100.00
ALWAYS32055100.00
CONT_ASSIGN37411100.00
ALWAYS38933100.00
CONT_ASSIGN39711100.00
ALWAYS4001717100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
185 1 1
186 1 1
188 1 1
191 1 1
192 1 1
MISSING_ELSE
198 1 1
199 1 1
MISSING_ELSE
204 1 1
205 0 1
MISSING_ELSE
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 0 1
MISSING_ELSE
223 1 1
224 1 1
234 1 1
242 2 2
243 2 2
MISSING_ELSE
248 1 1
250 1 1
252 1 1
256 1 1
MISSING_ELSE
MISSING_ELSE
264 1 1
266 1 1
267 1 1
268 1 1
MISSING_ELSE
MISSING_ELSE
302 unreachable
307 1 1
308 1 1
309 1 1
310 1 1
311 1 1
312 1 1
320 1 1
322 1 1
324 1 1
335 1 1
347 1 1
357 unreachable
374 1 1
389 3 3
397 1 1
400 1 1
402 1 1
404 1 1
407 1 1
MISSING_ELSE
412 1 1
413 1 1
MISSING_ELSE
418 1 1
419 1 1
MISSING_ELSE
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
432 1 1
433 1 1
MISSING_ELSE
439 1 1
451 1 1
452 1 1
MISSING_ELSE


Cond Coverage for Module : kmac_errchk
TotalCoveredPercent
Conditions605896.67
Logical605896.67
Non-Logical00
Event00

 LINE       204
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       217
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------
-1-StatusTests
0CoveredT3,T14,T16
1Not Covered

 LINE       234
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010CoveredT25,T30,T49
100CoveredT25,T50,T30

 LINE       234
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T30,T49
11CoveredT25,T30,T49

 LINE       250
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       250
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       250
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )
-1-StatusTests
0CoveredT25,T30,T49
1CoveredT1,T2,T3

 LINE       252
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))
-1--2-StatusTests
00CoveredT25,T30,T49
01CoveredT1,T2,T3
10CoveredT2,T13,T14

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T30,T49
11CoveredT2,T13,T14

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T13,T14

 LINE       252
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT14,T17,T25
10CoveredT25,T30,T49
11CoveredT1,T2,T3

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------
-1--2-StatusTests
00CoveredT2,T13,T14
01CoveredT1,T2,T3
10CoveredT2,T3,T14

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------
-1-StatusTests
0CoveredT2,T3,T13
1CoveredT1,T2,T3

 LINE       266
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT2,T3,T13
111CoveredT1,T2,T3

 LINE       266
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       266
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       267
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T50,T30

 LINE       397
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T50,T30

 LINE       404
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------
-1--2-StatusTests
01CoveredT25,T30,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       404
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       412
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       424
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T14,T16

 LINE       426
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : kmac_errchk
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 10 90.91
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorbed 419 Covered T1,T2,T3
StIdle 427 Covered T1,T2,T3
StMsgFeed 407 Covered T1,T2,T3
StProcessing 413 Covered T1,T2,T3
StSqueezing 425 Covered T3,T14,T16
StTerminalError 452 Covered T4,T5,T6


transitionsLine No.CoveredTests
StAbsorbed->StIdle 427 Covered T1,T2,T3
StAbsorbed->StSqueezing 425 Covered T3,T14,T16
StAbsorbed->StTerminalError 452 Covered T58,T59,T60
StIdle->StMsgFeed 407 Covered T1,T2,T3
StIdle->StTerminalError 452 Covered T10,T7,T32
StMsgFeed->StProcessing 413 Covered T1,T2,T3
StMsgFeed->StTerminalError 452 Covered T4,T5,T6
StProcessing->StAbsorbed 419 Covered T1,T2,T3
StProcessing->StTerminalError 452 Covered T9
StSqueezing->StAbsorbed 433 Covered T3,T14,T16
StSqueezing->StTerminalError 452 Not Covered



Branch Coverage for Module : kmac_errchk
Line No.TotalCoveredPercent
Branches 50 48 96.00
TERNARY 397 2 2 100.00
CASE 188 12 10 83.33
IF 242 3 3 100.00
IF 250 3 3 100.00
IF 266 3 3 100.00
CASE 307 6 6 100.00
CASE 322 4 4 100.00
IF 389 2 2 100.00
CASE 402 13 13 100.00
IF 451 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 397 (block_swcmd) ?

Branches:
-1-StatusTests
1 Covered T25,T50,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 188 case (st) -2-: 191 if ((!(sw_cmd_i inside {CmdNone, CmdStart}))) -3-: 198 if ((!(sw_cmd_i inside {CmdNone, CmdProcess}))) -4-: 204 if ((sw_cmd_i != CmdNone)) -5-: 211 if ((!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone}))) -6-: 217 if ((sw_cmd_i != CmdNone))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle 1 - - - - Covered T25,T30,T49
StIdle 0 - - - - Covered T1,T2,T3
StMsgFeed - 1 - - - Covered T25,T30,T49
StMsgFeed - 0 - - - Covered T1,T2,T3
StProcessing - - 1 - - Not Covered
StProcessing - - 0 - - Covered T1,T2,T3
StAbsorbed - - - 1 - Covered T25,T50,T30
StAbsorbed - - - 0 - Covered T1,T2,T3
StSqueezing - - - - 1 Not Covered
StSqueezing - - - - 0 Covered T3,T14,T16
StTerminalError - - - - - Covered T4,T5,T6
default - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 242 if ((!rst_ni)) -2-: 243 if ((!block_swcmd))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T25,T50,T30


LineNo. Expression -1-: 250 if (((st == StIdle) && (st_d == StMsgFeed))) -2-: 252 if ((!(((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))))

Branches:
-1--2-StatusTests
1 1 Covered T25,T30,T49
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 266 if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i)) -2-: 267 if ((cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC))

Branches:
-1--2-StatusTests
1 1 Covered T25,T50,T30
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 307 case (st)

Branches:
-1-StatusTests
StIdle Covered T1,T2,T3
StMsgFeed Covered T1,T2,T3
StProcessing Covered T1,T2,T3
StAbsorbed Covered T1,T2,T3
StSqueezing Covered T3,T14,T16
default Covered T4,T5,T6


LineNo. Expression -1-: 322 case (1'b1)

Branches:
-1-StatusTests
err_swsequence Covered T25,T50,T30
err_modestrength Covered T25,T30,T49
err_prefix Covered T25,T50,T30
err_entropy_ready Unreachable
default Covered T1,T2,T3


LineNo. Expression -1-: 389 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 case (st) -2-: 404 if (((!app_active_i) && (sw_cmd_i == CmdStart))) -3-: 412 if ((sw_cmd_i == CmdProcess)) -4-: 418 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i)) -5-: 424 if ((sw_cmd_i == CmdManualRun)) -6-: 426 if ((sw_cmd_i == CmdDone)) -7-: 432 if (keccak_done_i)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle 1 - - - - - Covered T1,T2,T3
StIdle 0 - - - - - Covered T1,T2,T3
StMsgFeed - 1 - - - - Covered T1,T2,T3
StMsgFeed - 0 - - - - Covered T1,T2,T3
StProcessing - - 1 - - - Covered T1,T2,T3
StProcessing - - 0 - - - Covered T1,T2,T3
StAbsorbed - - - 1 - - Covered T3,T14,T16
StAbsorbed - - - 0 1 - Covered T1,T2,T3
StAbsorbed - - - 0 0 - Covered T1,T2,T3
StSqueezing - - - - - 1 Covered T3,T14,T16
StSqueezing - - - - - 0 Covered T3,T14,T16
StTerminalError - - - - - - Covered T4,T5,T6
default - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 451 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


Assert Coverage for Module : kmac_errchk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ExpectedModeStrengthBits_A 1034 1034 0 0
ExpectedStSwCmdBits_A 1034 1034 0 0
StKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ExpectedModeStrengthBits_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1034 1034 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

ExpectedStSwCmdBits_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1034 1034 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

StKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 5839 5743 0 0
T2 16973 16880 0 0
T3 246640 246582 0 0
T13 642597 642589 0 0
T14 354027 354020 0 0
T15 24378 24312 0 0
T16 492694 492616 0 0
T17 685361 685286 0 0
T20 1046 974 0 0
T21 1642 1558 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 5839 5743 0 0
T2 16973 16880 0 0
T3 246640 246582 0 0
T13 642597 642589 0 0
T14 354027 354020 0 0
T15 24378 24312 0 0
T16 492694 492616 0 0
T17 685361 685286 0 0
T20 1046 974 0 0
T21 1642 1558 0 0

Line Coverage for Instance : tb.dut.u_errchk
Line No.TotalCoveredPercent
TOTAL615996.72
ALWAYS185151386.67
CONT_ASSIGN23411100.00
ALWAYS24244100.00
ALWAYS24844100.00
ALWAYS26444100.00
CONT_ASSIGN30200
ALWAYS30766100.00
ALWAYS32055100.00
CONT_ASSIGN37411100.00
ALWAYS38933100.00
CONT_ASSIGN39711100.00
ALWAYS4001717100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
185 1 1
186 1 1
188 1 1
191 1 1
192 1 1
MISSING_ELSE
198 1 1
199 1 1
MISSING_ELSE
204 1 1
205 0 1
MISSING_ELSE
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 0 1
MISSING_ELSE
223 1 1
224 1 1
234 1 1
242 2 2
243 2 2
MISSING_ELSE
248 1 1
250 1 1
252 1 1
256 1 1
MISSING_ELSE
MISSING_ELSE
264 1 1
266 1 1
267 1 1
268 1 1
MISSING_ELSE
MISSING_ELSE
302 unreachable
307 1 1
308 1 1
309 1 1
310 1 1
311 1 1
312 1 1
320 1 1
322 1 1
324 1 1
335 1 1
347 1 1
357 unreachable
374 1 1
389 3 3
397 1 1
400 1 1
402 1 1
404 1 1
407 1 1
MISSING_ELSE
412 1 1
413 1 1
MISSING_ELSE
418 1 1
419 1 1
MISSING_ELSE
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
432 1 1
433 1 1
MISSING_ELSE
439 1 1
451 1 1
452 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_errchk
TotalCoveredPercent
Conditions605896.67
Logical605896.67
Non-Logical00
Event00

 LINE       204
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       217
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------
-1-StatusTests
0CoveredT3,T14,T16
1Not Covered

 LINE       234
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010CoveredT25,T30,T49
100CoveredT25,T50,T30

 LINE       234
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T30,T49
11CoveredT25,T30,T49

 LINE       250
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       250
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       250
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )
-1-StatusTests
0CoveredT25,T30,T49
1CoveredT1,T2,T3

 LINE       252
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))
-1--2-StatusTests
00CoveredT25,T30,T49
01CoveredT1,T2,T3
10CoveredT2,T13,T14

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T30,T49
11CoveredT2,T13,T14

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T13,T14

 LINE       252
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT14,T17,T25
10CoveredT25,T30,T49
11CoveredT1,T2,T3

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------
-1--2-StatusTests
00CoveredT2,T13,T14
01CoveredT1,T2,T3
10CoveredT2,T3,T14

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------
-1-StatusTests
0CoveredT2,T3,T13
1CoveredT1,T2,T3

 LINE       266
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT2,T3,T13
111CoveredT1,T2,T3

 LINE       266
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       266
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       267
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T50,T30

 LINE       397
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T50,T30

 LINE       404
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------
-1--2-StatusTests
01CoveredT25,T30,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       404
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       412
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       424
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T14,T16

 LINE       426
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_errchk
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 10 10 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorbed 419 Covered T1,T2,T3
StIdle 427 Covered T1,T2,T3
StMsgFeed 407 Covered T1,T2,T3
StProcessing 413 Covered T1,T2,T3
StSqueezing 425 Covered T3,T14,T16
StTerminalError 452 Covered T4,T5,T6


transitionsLine No.CoveredTestsExclude Annotation
StAbsorbed->StIdle 427 Covered T1,T2,T3
StAbsorbed->StSqueezing 425 Covered T3,T14,T16
StAbsorbed->StTerminalError 452 Covered T58,T59,T60
StIdle->StMsgFeed 407 Covered T1,T2,T3
StIdle->StTerminalError 452 Covered T10,T7,T32
StMsgFeed->StProcessing 413 Covered T1,T2,T3
StMsgFeed->StTerminalError 452 Covered T4,T5,T6
StProcessing->StAbsorbed 419 Covered T1,T2,T3
StProcessing->StTerminalError 452 Covered T9
StSqueezing->StAbsorbed 433 Covered T3,T14,T16
StSqueezing->StTerminalError 452 Excluded [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.



Branch Coverage for Instance : tb.dut.u_errchk
Line No.TotalCoveredPercent
Branches 50 48 96.00
TERNARY 397 2 2 100.00
CASE 188 12 10 83.33
IF 242 3 3 100.00
IF 250 3 3 100.00
IF 266 3 3 100.00
CASE 307 6 6 100.00
CASE 322 4 4 100.00
IF 389 2 2 100.00
CASE 402 13 13 100.00
IF 451 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 397 (block_swcmd) ?

Branches:
-1-StatusTests
1 Covered T25,T50,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 188 case (st) -2-: 191 if ((!(sw_cmd_i inside {CmdNone, CmdStart}))) -3-: 198 if ((!(sw_cmd_i inside {CmdNone, CmdProcess}))) -4-: 204 if ((sw_cmd_i != CmdNone)) -5-: 211 if ((!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone}))) -6-: 217 if ((sw_cmd_i != CmdNone))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle 1 - - - - Covered T25,T30,T49
StIdle 0 - - - - Covered T1,T2,T3
StMsgFeed - 1 - - - Covered T25,T30,T49
StMsgFeed - 0 - - - Covered T1,T2,T3
StProcessing - - 1 - - Not Covered
StProcessing - - 0 - - Covered T1,T2,T3
StAbsorbed - - - 1 - Covered T25,T50,T30
StAbsorbed - - - 0 - Covered T1,T2,T3
StSqueezing - - - - 1 Not Covered
StSqueezing - - - - 0 Covered T3,T14,T16
StTerminalError - - - - - Covered T4,T5,T6
default - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 242 if ((!rst_ni)) -2-: 243 if ((!block_swcmd))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T25,T50,T30


LineNo. Expression -1-: 250 if (((st == StIdle) && (st_d == StMsgFeed))) -2-: 252 if ((!(((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))))

Branches:
-1--2-StatusTests
1 1 Covered T25,T30,T49
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 266 if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i)) -2-: 267 if ((cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC))

Branches:
-1--2-StatusTests
1 1 Covered T25,T50,T30
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 307 case (st)

Branches:
-1-StatusTests
StIdle Covered T1,T2,T3
StMsgFeed Covered T1,T2,T3
StProcessing Covered T1,T2,T3
StAbsorbed Covered T1,T2,T3
StSqueezing Covered T3,T14,T16
default Covered T4,T5,T6


LineNo. Expression -1-: 322 case (1'b1)

Branches:
-1-StatusTests
err_swsequence Covered T25,T50,T30
err_modestrength Covered T25,T30,T49
err_prefix Covered T25,T50,T30
err_entropy_ready Unreachable
default Covered T1,T2,T3


LineNo. Expression -1-: 389 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 case (st) -2-: 404 if (((!app_active_i) && (sw_cmd_i == CmdStart))) -3-: 412 if ((sw_cmd_i == CmdProcess)) -4-: 418 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i)) -5-: 424 if ((sw_cmd_i == CmdManualRun)) -6-: 426 if ((sw_cmd_i == CmdDone)) -7-: 432 if (keccak_done_i)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle 1 - - - - - Covered T1,T2,T3
StIdle 0 - - - - - Covered T1,T2,T3
StMsgFeed - 1 - - - - Covered T1,T2,T3
StMsgFeed - 0 - - - - Covered T1,T2,T3
StProcessing - - 1 - - - Covered T1,T2,T3
StProcessing - - 0 - - - Covered T1,T2,T3
StAbsorbed - - - 1 - - Covered T3,T14,T16
StAbsorbed - - - 0 1 - Covered T1,T2,T3
StAbsorbed - - - 0 0 - Covered T1,T2,T3
StSqueezing - - - - - 1 Covered T3,T14,T16
StSqueezing - - - - - 0 Covered T3,T14,T16
StTerminalError - - - - - - Covered T4,T5,T6
default - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 451 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_errchk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ExpectedModeStrengthBits_A 1034 1034 0 0
ExpectedStSwCmdBits_A 1034 1034 0 0
StKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ExpectedModeStrengthBits_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1034 1034 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

ExpectedStSwCmdBits_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1034 1034 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

StKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 5839 5743 0 0
T2 16973 16880 0 0
T3 246640 246582 0 0
T13 642597 642589 0 0
T14 354027 354020 0 0
T15 24378 24312 0 0
T16 492694 492616 0 0
T17 685361 685286 0 0
T20 1046 974 0 0
T21 1642 1558 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 5839 5743 0 0
T2 16973 16880 0 0
T3 246640 246582 0 0
T13 642597 642589 0 0
T14 354027 354020 0 0
T15 24378 24312 0 0
T16 492694 492616 0 0
T17 685361 685286 0 0
T20 1046 974 0 0
T21 1642 1558 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%