Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254281374	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199995520

1

T1

11571

T2

887539

T3

95022

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239729160	1			T1	13412		T2	111049		T3	115373
values[0x0]	103099257	1			T1	3290		T2	450162		T3	48508
values[0x1]	111448477	1			T1	3603		T2	488836		T3	52335

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198229235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

256047659

1

T1

13644

T2

114403

T3

120794

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1349533	1			T1	64		T2	8091		T3	844
valid_sources[0x01]	1350550	1			T1	82		T2	7902		T3	867
valid_sources[0x02]	1345558	1			T1	89		T2	8077		T3	989
valid_sources[0x03]	3862591	1			T1	70		T2	8619		T3	885
valid_sources[0x04]	3741549	1			T1	82		T2	7815		T3	936
valid_sources[0x05]	1355446	1			T1	74		T2	8181		T3	744
valid_sources[0x06]	1416641	1			T1	72		T2	8524		T3	816
valid_sources[0x07]	1522395	1			T1	84		T2	8336		T3	687
valid_sources[0x08]	1348302	1			T1	78		T2	7386		T3	849
valid_sources[0x09]	1351953	1			T1	85		T2	8151		T3	977
valid_sources[0x0a]	1368726	1			T1	83		T2	7746		T3	958
valid_sources[0x0b]	1513607	1			T1	79		T2	7965		T3	704
valid_sources[0x0c]	1343589	1			T1	83		T2	7958		T3	810
valid_sources[0x0d]	1351635	1			T1	78		T2	8091		T3	741
valid_sources[0x0e]	1833872	1			T1	71		T2	7823		T3	949
valid_sources[0x0f]	2212737	1			T1	97		T2	7956		T3	857
valid_sources[0x10]	1805726	1			T1	77		T2	8611		T3	801
valid_sources[0x11]	2486240	1			T1	82		T2	8227		T3	613
valid_sources[0x12]	1348877	1			T1	69		T2	7689		T3	836
valid_sources[0x13]	1348244	1			T1	74		T2	7555		T3	939
valid_sources[0x14]	1356080	1			T1	76		T2	7909		T3	704
valid_sources[0x15]	1419341	1			T1	80		T2	8068		T3	696
valid_sources[0x16]	1346455	1			T1	72		T2	8202		T3	517
valid_sources[0x17]	1353461	1			T1	75		T2	8335		T3	680
valid_sources[0x18]	2410441	1			T1	96		T2	8150		T3	1147
valid_sources[0x19]	3414590	1			T1	73		T2	8167		T3	823
valid_sources[0x1a]	1351635	1			T1	88		T2	7291		T3	751
valid_sources[0x1b]	2046969	1			T1	81		T2	7999		T3	567
valid_sources[0x1c]	2214675	1			T1	81		T2	8099		T3	1220
valid_sources[0x1d]	3358762	1			T1	61		T2	7972		T3	850
valid_sources[0x1e]	1448044	1			T1	85		T2	8336		T3	764
valid_sources[0x1f]	1373201	1			T1	74		T2	8035		T3	554
valid_sources[0x20]	4404499	1			T1	86		T2	7842		T3	896
valid_sources[0x21]	1355436	1			T1	83		T2	7906		T3	867
valid_sources[0x22]	2601842	1			T1	71		T2	7974		T3	898
valid_sources[0x23]	1353398	1			T1	82		T2	8177		T3	683
valid_sources[0x24]	1361494	1			T1	91		T2	7785		T3	819
valid_sources[0x25]	1364165	1			T1	70		T2	8332		T3	712
valid_sources[0x26]	1349040	1			T1	61		T2	7753		T3	980
valid_sources[0x27]	1527841	1			T1	87		T2	7910		T3	922
valid_sources[0x28]	1652838	1			T1	104		T2	7702		T3	776
valid_sources[0x29]	1346408	1			T1	79		T2	7450		T3	602
valid_sources[0x2a]	1347868	1			T1	83		T2	7955		T3	768
valid_sources[0x2b]	4239541	1			T1	90		T2	8367		T3	795
valid_sources[0x2c]	1376669	1			T1	73		T2	7953		T3	847
valid_sources[0x2d]	1347375	1			T1	79		T2	8122		T3	893
valid_sources[0x2e]	1561305	1			T1	88		T2	7735		T3	862
valid_sources[0x2f]	1348292	1			T1	69		T2	8021		T3	735
valid_sources[0x30]	1526707	1			T1	70		T2	8494		T3	864
valid_sources[0x31]	1350572	1			T1	67		T2	7533		T3	601
valid_sources[0x32]	1354089	1			T1	92		T2	8300		T3	869
valid_sources[0x33]	3383971	1			T1	73		T2	7986		T3	834
valid_sources[0x34]	2015063	1			T1	94		T2	8151		T3	692
valid_sources[0x35]	1345030	1			T1	75		T2	8000		T3	740
valid_sources[0x36]	1346322	1			T1	84		T2	8561		T3	702
valid_sources[0x37]	1347611	1			T1	81		T2	8335		T3	938
valid_sources[0x38]	1350086	1			T1	71		T2	7979		T3	943
valid_sources[0x39]	1349334	1			T1	64		T2	8622		T3	810
valid_sources[0x3a]	1406762	1			T1	69		T2	7652		T3	801
valid_sources[0x3b]	1404099	1			T1	74		T2	7816		T3	881
valid_sources[0x3c]	1431589	1			T1	99		T2	7957		T3	759
valid_sources[0x3d]	1352034	1			T1	77		T2	8089		T3	896
valid_sources[0x3e]	1345619	1			T1	69		T2	7720		T3	958
valid_sources[0x3f]	1344364	1			T1	86		T2	7806		T3	990
valid_sources[0x40]	2173758	1			T1	86		T2	8345		T3	970
valid_sources[0x41]	1351889	1			T1	74		T2	8224		T3	1183
valid_sources[0x42]	3798254	1			T1	99		T2	8026		T3	942
valid_sources[0x43]	1346799	1			T1	75		T2	8271		T3	579
valid_sources[0x44]	1346491	1			T1	72		T2	7728		T3	793
valid_sources[0x45]	2317433	1			T1	66		T2	7426		T3	982
valid_sources[0x46]	1811905	1			T1	72		T2	7915		T3	617
valid_sources[0x47]	1400536	1			T1	77		T2	7415		T3	825
valid_sources[0x48]	1353404	1			T1	68		T2	8136		T3	892
valid_sources[0x49]	1347187	1			T1	67		T2	7678		T3	799
valid_sources[0x4a]	1807218	1			T1	85		T2	8014		T3	744
valid_sources[0x4b]	1357593	1			T1	81		T2	7945		T3	614
valid_sources[0x4c]	3768123	1			T1	77		T2	8248		T3	870
valid_sources[0x4d]	2112569	1			T1	67		T2	8085		T3	846
valid_sources[0x4e]	1346694	1			T1	95		T2	7908		T3	1007
valid_sources[0x4f]	1444555	1			T1	90		T2	8256		T3	1219
valid_sources[0x50]	1406500	1			T1	81		T2	7474		T3	724
valid_sources[0x51]	1351218	1			T1	67		T2	8028		T3	929
valid_sources[0x52]	1808557	1			T1	86		T2	7873		T3	795
valid_sources[0x53]	1344849	1			T1	79		T2	8040		T3	1102
valid_sources[0x54]	1357539	1			T1	63		T2	8209		T3	803
valid_sources[0x55]	1349263	1			T1	88		T2	8083		T3	778
valid_sources[0x56]	1350391	1			T1	77		T2	8006		T3	882
valid_sources[0x57]	1811436	1			T1	80		T2	7761		T3	846
valid_sources[0x58]	1371245	1			T1	89		T2	7826		T3	865
valid_sources[0x59]	1350643	1			T1	74		T2	8169		T3	761
valid_sources[0x5a]	1877212	1			T1	74		T2	7349		T3	842
valid_sources[0x5b]	1356127	1			T1	76		T2	7845		T3	929
valid_sources[0x5c]	2213832	1			T1	83		T2	8272		T3	793
valid_sources[0x5d]	3764929	1			T1	78		T2	7687		T3	693
valid_sources[0x5e]	2261518	1			T1	78		T2	8052		T3	622
valid_sources[0x5f]	2229148	1			T1	107		T2	7795		T3	691
valid_sources[0x60]	1357804	1			T1	69		T2	8035		T3	996
valid_sources[0x61]	2279743	1			T1	76		T2	7648		T3	736
valid_sources[0x62]	2302595	1			T1	81		T2	8305		T3	831
valid_sources[0x63]	2042103	1			T1	87		T2	7953		T3	813
valid_sources[0x64]	2203040	1			T1	83		T2	8175		T3	761
valid_sources[0x65]	1349944	1			T1	69		T2	7755		T3	1037
valid_sources[0x66]	1398139	1			T1	79		T2	7608		T3	885
valid_sources[0x67]	1352352	1			T1	81		T2	7737		T3	695
valid_sources[0x68]	2239490	1			T1	68		T2	7645		T3	975
valid_sources[0x69]	3803004	1			T1	81		T2	7668		T3	778
valid_sources[0x6a]	1351943	1			T1	55		T2	7694		T3	847
valid_sources[0x6b]	1356767	1			T1	72		T2	8212		T3	856
valid_sources[0x6c]	1344577	1			T1	74		T2	7960		T3	614
valid_sources[0x6d]	1351393	1			T1	69		T2	7881		T3	756
valid_sources[0x6e]	1346509	1			T1	89		T2	7587		T3	800
valid_sources[0x6f]	1430096	1			T1	76		T2	8085		T3	654
valid_sources[0x70]	1391795	1			T1	90		T2	7650		T3	794
valid_sources[0x71]	1406182	1			T1	67		T2	8577		T3	941
valid_sources[0x72]	1348967	1			T1	67		T2	8018		T3	952
valid_sources[0x73]	1350281	1			T1	64		T2	8333		T3	913
valid_sources[0x74]	1356526	1			T1	92		T2	7657		T3	655
valid_sources[0x75]	1450084	1			T1	75		T2	7630		T3	890
valid_sources[0x76]	1420099	1			T1	85		T2	8412		T3	652
valid_sources[0x77]	3032607	1			T1	65		T2	8174		T3	956
valid_sources[0x78]	1349247	1			T1	79		T2	7786		T3	821
valid_sources[0x79]	1358191	1			T1	61		T2	7359		T3	625
valid_sources[0x7a]	1353615	1			T1	65		T2	8222		T3	993
valid_sources[0x7b]	1927662	1			T1	74		T2	8509		T3	745
valid_sources[0x7c]	1415091	1			T1	72		T2	8123		T3	979
valid_sources[0x7d]	5287494	1			T1	104		T2	8088		T3	860
valid_sources[0x7e]	2215014	1			T1	65		T2	8196		T3	970
valid_sources[0x7f]	1345985	1			T1	82		T2	8075		T3	809
valid_sources[0x80]	2540598	1			T1	70		T2	8178		T3	1229

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87125522

1

T1

8040

T2

420223

T3

40747

values[0x0]

all_enables

biggest_size

60719392

1

T1

1869

T2

253417

T3

28912

values[0x1]

all_enables

biggest_size

52150606

1

T1

1662

T2

213899

T3

25363