Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255406295

1

T1

8734

T2

116195

T3

121194

full_word

200066486

1

T1

11571

T2

887539

T3

95022

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455472501	1			T1	20305		T2	204948		T3	216216
auto[TlIntgErrCmd]	86	1			T96	2		T97	5		T98	4
auto[TlIntgErrData]	95	1			T96	3		T97	4		T98	2
auto[TlIntgErrBoth]	99	1			T96	5		T97	1		T98	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239946471

1

T1

13412

T2

111049

T3

115373

auto[1]

215526310

1

T1

6893

T2

938998

T3

100843

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152803046	1			T1	5372		T2	690268		T3	74626
auto[TlIntgErrNone]	partial	auto[1]	102602984	1			T1	3362		T2	471682		T3	46568
auto[TlIntgErrNone]	full_word	auto[0]	87143300	1			T1	8040		T2	420223		T3	40747
auto[TlIntgErrNone]	full_word	auto[1]	112923171	1			T1	3531		T2	467316		T3	54275
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T97	3		T98	2		T153	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T96	2		T97	2		T98	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T151	1		T155	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T153	1		T152	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T96	3		T97	3		T98	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T97	1		T98	1		T153	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T156	2		T155	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T151	1		T152	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T96	2		T98	1		T153	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T96	3		T97	1		T98	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T157	1		T156	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T154	1		-	-		-	-