Module Definition
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Module : kmac_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.96 98.55 92.86 87.50 92.00 88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_kmac_core 91.96 98.55 92.86 87.50 92.00 88.89



Module Instance : tb.dut.u_kmac_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.96 98.55 92.86 87.50 92.00 88.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.72 98.75 92.86 100.00 87.50 92.31 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_key_slicer[0].u_key_slicer 100.00 100.00 100.00
u_key_index_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_core
Line No.TotalCoveredPercent
TOTAL696898.55
CONT_ASSIGN15111100.00
ALWAYS15933100.00
ALWAYS1643030100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN26311100.00
ALWAYS2666583.33
CONT_ASSIGN28511100.00
ALWAYS30566100.00
ALWAYS33666100.00
CONT_ASSIGN37011100.00
CONT_ASSIGN39211100.00
ALWAYS41866100.00
CONT_ASSIGN42911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
159 3 3
164 1 1
166 1 1
167 1 1
169 1 1
171 1 1
172 1 1
174 1 1
176 1 1
178 1 1
179 1 1
181 1 1
188 1 1
189 1 1
191 1 1
192 1 1
194 1 1
195 1 1
197 1 1
199 1 1
205 1 1
206 1 1
208 1 1
210 1 1
215 1 1
216 1 1
218 1 1
224 1 1
225 1 1
238 1 1
239 1 1
MISSING_ELSE
249 1 1
250 1 1
251 1 1
252 1 1
256 1 1
258 1 1
263 1 1
266 1 1
267 1 1
268 1 1
269 0 1
270 1 1
272 1 1
MISSING_ELSE
285 1 1
305 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
336 1 1
339 1 1
343 1 1
347 1 1
351 1 1
356 1 1
370 1 1
392 1 1
418 1 1
419 1 1
420 1 1
421 1 1
422 1 1
423 1 1
429 1 1


Cond Coverage for Module : kmac_core
TotalCoveredPercent
Conditions282692.86
Logical282692.86
Non-Logical00
Event00

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T12
11CoveredT1,T3,T12

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------
-1--2-StatusTests
00CoveredT1,T3,T12
01Not Covered
10CoveredT1,T3,T12

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T12
11CoveredT1,T3,T12

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T12

FSM Coverage for Module : kmac_core
Summary for FSM :: st
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 7 87.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StKey 179 Covered T1,T3,T12
StKmacFlush 206 Covered T1,T3,T12
StKmacIdle 181 Covered T1,T2,T3
StKmacMsg 192 Covered T1,T3,T12
StTerminalError 239 Covered T4,T5,T6


transitionsLine No.CoveredTests
StKey->StKmacMsg 192 Covered T1,T3,T12
StKey->StTerminalError 239 Covered T32,T52,T8
StKmacFlush->StKmacIdle 216 Covered T1,T3,T12
StKmacFlush->StTerminalError 239 Not Covered
StKmacIdle->StKey 179 Covered T1,T3,T12
StKmacIdle->StTerminalError 239 Covered T4,T5,T7
StKmacMsg->StKmacFlush 206 Covered T1,T3,T12
StKmacMsg->StTerminalError 239 Covered T6,T51,T67



Branch Coverage for Module : kmac_core
Line No.TotalCoveredPercent
Branches 50 46 92.00
TERNARY 249 2 2 100.00
TERNARY 250 2 2 100.00
TERNARY 251 2 2 100.00
TERNARY 252 2 2 100.00
TERNARY 256 2 2 100.00
TERNARY 258 2 2 100.00
TERNARY 263 2 2 100.00
IF 159 2 2 100.00
CASE 176 10 10 100.00
IF 238 2 2 100.00
IF 266 4 3 75.00
CASE 305 6 5 83.33
CASE 418 6 5 83.33
CASE 336 6 5 83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 249 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 250 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 251 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 256 (en_key_write) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 258 (en_key_write) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 263 (kmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 159 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 176 case (st) -2-: 178 if ((kmac_en_i && start_i)) -3-: 191 if (sent_blocksize) -4-: 205 if ((process_i || process_latched)) -5-: 215 if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:
-1--2--3--4--5-StatusTests
StKmacIdle 1 - - - Covered T1,T3,T12
StKmacIdle 0 - - - Covered T1,T2,T3
StKey - 1 - - Covered T1,T3,T12
StKey - 0 - - Covered T1,T3,T12
StKmacMsg - - 1 - Covered T1,T3,T12
StKmacMsg - - 0 - Covered T1,T3,T12
StKmacFlush - - - 1 Covered T1,T3,T12
StKmacFlush - - - 0 Covered T1,T3,T12
StTerminalError - - - - Covered T4,T5,T6
default - - - - Covered T4,T10,T11


LineNo. Expression -1-: 238 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 266 if ((!rst_ni)) -2-: 268 if ((process_i && (!process_o))) -3-: 270 if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 305 case (key_len_i)

Branches:
-1-StatusTests
Key128 Covered T1,T2,T3
Key192 Covered T1,T2,T3
Key256 Covered T1,T2,T3
Key384 Covered T1,T2,T3
Key512 Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 418 case (strength_i)

Branches:
-1-StatusTests
L128 Covered T1,T2,T3
L224 Covered T12,T13,T16
L256 Covered T1,T2,T3
L384 Covered T12,T13,T16
L512 Covered T12,T13,T14
default Not Covered


LineNo. Expression -1-: 336 case (key_len_i)

Branches:
-1-StatusTests
Key128 Covered T1,T2,T3
Key192 Covered T1,T2,T3
Key256 Covered T1,T2,T3
Key384 Covered T1,T2,T3
Key512 Covered T1,T2,T3
default Not Covered


Assert Coverage for Module : kmac_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 8 88.89
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 8 88.89




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckOnlyInMessageState_A 2147483647 7819678 0 0
KeyDataStable_M 2147483647 508998 0 0
KeyLengthStable_M 2147483647 281863 0 0
KmacEnStable_M 2147483647 21649 0 0
MaxKeyLenMatchToKey512_A 1027 1027 0 0
ModeStable_M 2147483647 33119 0 0
ProcessLatchedCleared_A 2147483647 0 0 0
StrengthStable_M 2147483647 39700 0 0
u_state_regs_A 2147483647 2147483647 0 0


AckOnlyInMessageState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7819678 0 0
T1 44780 1051 0 0
T2 188790 0 0 0
T3 216773 16711 0 0
T12 145705 2589 0 0
T13 194361 38217 0 0
T14 328236 0 0 0
T15 73932 2594 0 0
T16 55470 240 0 0
T17 431706 0 0 0
T18 0 47796 0 0
T19 29559 0 0 0
T27 0 5224 0 0
T34 0 8596 0 0
T35 0 157 0 0

KeyDataStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 508998 0 0
T1 44780 196 0 0
T2 188790 0 0 0
T3 216773 448 0 0
T12 145705 676 0 0
T13 194361 2110 0 0
T14 328236 0 0 0
T15 73932 64 0 0
T16 55470 1344 0 0
T17 431706 0 0 0
T18 0 1296 0 0
T19 29559 90 0 0
T34 0 2288 0 0
T35 0 34 0 0

KeyLengthStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 281863 0 0
T1 44780 15 0 0
T2 188790 1805 0 0
T3 216773 31 0 0
T12 145705 44 0 0
T13 194361 163 0 0
T14 328236 196 0 0
T15 73932 3 0 0
T16 55470 85 0 0
T17 431706 1824 0 0
T19 29559 7 0 0

KmacEnStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 21649 0 0
T1 44780 7 0 0
T2 188790 0 0 0
T3 216773 21 0 0
T12 145705 20 0 0
T13 194361 72 0 0
T14 328236 0 0 0
T15 73932 2 0 0
T16 55470 41 0 0
T17 431706 0 0 0
T18 0 46 0 0
T19 29559 10 0 0
T34 0 57 0 0
T35 0 4 0 0

MaxKeyLenMatchToKey512_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T19 1 1 0 0

ModeStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 33119 0 0
T1 44780 9 0 0
T2 188790 1 0 0
T3 216773 21 0 0
T12 145705 29 0 0
T13 194361 90 0 0
T14 328236 0 0 0
T15 73932 2 0 0
T16 55470 43 0 0
T17 431706 1 0 0
T18 0 46 0 0
T19 29559 12 0 0

ProcessLatchedCleared_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

StrengthStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 39700 0 0
T1 44780 13 0 0
T2 188790 2 0 0
T3 216773 17 0 0
T12 145705 42 0 0
T13 194361 118 0 0
T14 328236 2 0 0
T15 73932 2 0 0
T16 55470 57 0 0
T17 431706 2 0 0
T19 29559 11 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 44780 44710 0 0
T2 188790 188789 0 0
T3 216773 216763 0 0
T12 145705 145611 0 0
T13 194361 194334 0 0
T14 328236 328226 0 0
T15 73932 73862 0 0
T16 55470 55411 0 0
T17 431706 431700 0 0
T19 29559 29479 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%