Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	264093	0	0
entropy_period_rd_A	2147483647	1469	0	0
intr_enable_rd_A	2147483647	2000	0	0
prefix_0_rd_A	2147483647	1342	0	0
prefix_10_rd_A	2147483647	1389	0	0
prefix_1_rd_A	2147483647	1269	0	0
prefix_2_rd_A	2147483647	1385	0	0
prefix_3_rd_A	2147483647	1329	0	0
prefix_4_rd_A	2147483647	1536	0	0
prefix_5_rd_A	2147483647	1572	0	0
prefix_6_rd_A	2147483647	1329	0	0
prefix_7_rd_A	2147483647	1467	0	0
prefix_8_rd_A	2147483647	1412	0	0
prefix_9_rd_A	2147483647	1355	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	264093	0	0
T47	408848	55048	0	0
T48	0	35508	0	0
T49	0	63776	0	0
T103	0	51032	0	0
T104	0	16572	0	0
T105	0	10299	0	0
T106	0	28737	0	0
T107	0	7	0	0
T108	0	18	0	0
T109	0	143	0	0
T110	141339	0	0	0
T111	148057	0	0	0
T112	34362	0	0	0
T113	5898	0	0	0
T114	34961	0	0	0
T115	718365	0	0	0
T116	183678	0	0	0
T117	175748	0	0	0
T118	326261	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1469	0	0
T79	11972	49	0	0
T97	12147	47	0	0
T125	3549	3	0	0
T126	4947	14	0	0
T127	10818	59	0	0
T128	73442	131	0	0
T129	1619	1	0	0
T130	1736	1	0	0
T131	1758	3	0	0
T132	11251	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2000	0	0
T97	12147	80	0	0
T107	7118	19	0	0
T125	3549	16	0	0
T126	4947	9	0	0
T127	10818	48	0	0
T128	73442	213	0	0
T129	1619	5	0	0
T130	1736	14	0	0
T133	770	10	0	0
T134	1762	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1342	0	0
T79	11972	54	0	0
T97	12147	46	0	0
T107	7118	9	0	0
T125	3549	2	0	0
T126	4947	11	0	0
T127	10818	16	0	0
T128	73442	228	0	0
T129	1619	5	0	0
T130	1736	3	0	0
T131	1758	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1389	0	0
T79	11972	58	0	0
T97	12147	36	0	0
T107	7118	9	0	0
T125	3549	8	0	0
T126	4947	14	0	0
T127	10818	13	0	0
T128	73442	233	0	0
T130	1736	6	0	0
T131	1758	4	0	0
T132	11251	78	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1269	0	0
T79	11972	46	0	0
T97	12147	56	0	0
T107	7118	4	0	0
T125	3549	7	0	0
T126	4947	5	0	0
T127	10818	35	0	0
T128	73442	186	0	0
T129	1619	4	0	0
T131	1758	2	0	0
T132	11251	25	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1385	0	0
T79	11972	50	0	0
T97	12147	53	0	0
T107	7118	10	0	0
T125	3549	1	0	0
T126	4947	2	0	0
T127	10818	81	0	0
T128	73442	199	0	0
T129	1619	9	0	0
T130	1736	8	0	0
T131	1758	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329	0	0
T79	11972	44	0	0
T97	12147	47	0	0
T107	7118	7	0	0
T125	3549	1	0	0
T126	4947	9	0	0
T127	10818	20	0	0
T128	73442	225	0	0
T129	1619	4	0	0
T130	1736	6	0	0
T131	1758	6	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1536	0	0
T79	11972	72	0	0
T97	12147	38	0	0
T125	3549	6	0	0
T126	4947	15	0	0
T127	10818	82	0	0
T128	73442	219	0	0
T129	1619	4	0	0
T130	1736	2	0	0
T131	1758	3	0	0
T132	11251	41	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1572	0	0
T79	11972	70	0	0
T97	12147	50	0	0
T107	7118	18	0	0
T125	3549	5	0	0
T126	4947	10	0	0
T127	10818	29	0	0
T128	73442	284	0	0
T130	1736	5	0	0
T131	1758	6	0	0
T132	11251	53	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329	0	0
T79	11972	59	0	0
T81	10125	20	0	0
T97	12147	43	0	0
T107	7118	2	0	0
T126	4947	6	0	0
T127	10818	31	0	0
T128	73442	187	0	0
T130	1736	8	0	0
T131	1758	8	0	0
T132	11251	68	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1467	0	0
T79	11972	68	0	0
T97	12147	47	0	0
T107	7118	10	0	0
T125	3549	4	0	0
T126	4947	4	0	0
T127	10818	84	0	0
T128	73442	233	0	0
T130	1736	6	0	0
T131	1758	1	0	0
T132	11251	53	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1412	0	0
T79	11972	62	0	0
T97	12147	49	0	0
T107	7118	16	0	0
T125	3549	3	0	0
T126	4947	2	0	0
T127	10818	27	0	0
T128	73442	231	0	0
T130	1736	4	0	0
T131	1758	8	0	0
T132	11251	61	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1355	0	0
T79	11972	52	0	0
T97	12147	60	0	0
T107	7118	2	0	0
T125	3549	5	0	0
T126	4947	13	0	0
T127	10818	28	0	0
T128	73442	239	0	0
T129	1619	4	0	0
T130	1736	3	0	0
T131	1758	7	0	0