Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257524269

1

T1

25

T2

17894

T3

25

full_word

200915289

1

T1

103

T2

97982

T3

126

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458439258	1			T1	128		T2	115876		T3	151
auto[TlIntgErrCmd]	99	1			T112	6		T113	3		T114	7
auto[TlIntgErrData]	95	1			T112	8		T113	7		T114	9
auto[TlIntgErrBoth]	106	1			T112	6		T113	10		T114	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241337123

1

T1

22

T2

36408

T3

58

auto[1]

217102435

1

T1

106

T2

79468

T3

93

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153813173	1			T1	17		T2	16811		T3	4
auto[TlIntgErrNone]	partial	auto[1]	103710824	1			T1	8		T2	1083		T3	21
auto[TlIntgErrNone]	full_word	auto[0]	87523818	1			T1	5		T2	19597		T3	54
auto[TlIntgErrNone]	full_word	auto[1]	113391443	1			T1	98		T2	78385		T3	72
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T112	2		T113	2		T114	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T112	4		T113	1		T114	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T172	1		T173	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T170	1		T172	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T112	3		T113	3		T114	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T112	4		T113	2		T114	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T112	1		T113	2		T176	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T114	2		T176	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T112	1		T113	3		T114	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T112	4		T113	5		T114	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T113	1		T171	1		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T112	1		T113	1		T114	1