Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_arbiter_fixed
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_app_intf.u_appid_arb 95.05 87.50 92.68 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL322887.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9711100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
CONT_ASSIGN124100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 3 3
87 0 3
89 3 3
97 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 0 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions413892.68
Logical413892.68
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT3,T4,T5
10CoveredT1,T9,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT3,T4,T13
10CoveredT1,T9,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT3,T4,T5
01Unreachable
10CoveredT3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT3,T4,T15
11CoveredT1,T9,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT13,T15,T19
11CoveredT1,T9,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T4,T5
10Not Covered
11CoveredT3,T4,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T9,T13
11CoveredT3,T4,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T9,T13
11CoveredT13,T15,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT3,T4,T15
11Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT1,T3,T4

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T3,T4


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T3,T4


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T3,T4


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T3,T4


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T3,T4,T5


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T3,T4,T5


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 1023 1023 0 0
GntImpliesReady_A 2147483647 7556 0 0
GntImpliesValid_A 2147483647 7556 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 7556 0 0
NoReadyValidNoGrant_A 2147483647 2147483647 0 0
Priority_A 2147483647 2272701 0 0
ReadyAndValidImplyGrant_A 2147483647 7556 0 0
ReqAndReadyImplyGrant_A 2147483647 7556 0 0
ReqImpliesValid_A 2147483647 2272701 0 0
ValidKnown_A 2147483647 2147483647 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14131 14075 0 0
T2 242183 242107 0 0
T3 4568 4405 0 0
T4 2228 2072 0 0
T5 3457 3307 0 0
T9 76326 76260 0 0
T11 138958 138949 0 0
T12 16136 16058 0 0
T13 166534 166480 0 0
T14 187095 187085 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7556 0 0
T1 14131 2 0 0
T2 242183 0 0 0
T3 4568 1 0 0
T4 2228 1 0 0
T5 3457 0 0 0
T9 76326 10 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 9 0 0
T14 187095 0 0 0
T15 0 18 0 0
T19 0 46 0 0
T23 0 110 0 0
T24 0 6 0 0
T36 0 6 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7556 0 0
T1 14131 2 0 0
T2 242183 0 0 0
T3 4568 1 0 0
T4 2228 1 0 0
T5 3457 0 0 0
T9 76326 10 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 9 0 0
T14 187095 0 0 0
T15 0 18 0 0
T19 0 46 0 0
T23 0 110 0 0
T24 0 6 0 0
T36 0 6 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14131 14075 0 0
T2 242183 242107 0 0
T3 4568 4405 0 0
T4 2228 2072 0 0
T5 3457 3307 0 0
T9 76326 76260 0 0
T11 138958 138949 0 0
T12 16136 16058 0 0
T13 166534 166480 0 0
T14 187095 187085 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14131 14075 0 0
T2 242183 242107 0 0
T3 4568 4405 0 0
T4 2228 2072 0 0
T5 3457 3307 0 0
T9 76326 76260 0 0
T11 138958 138949 0 0
T12 16136 16058 0 0
T13 166534 166480 0 0
T14 187095 187085 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7556 0 0
T1 14131 2 0 0
T2 242183 0 0 0
T3 4568 1 0 0
T4 2228 1 0 0
T5 3457 0 0 0
T9 76326 10 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 9 0 0
T14 187095 0 0 0
T15 0 18 0 0
T19 0 46 0 0
T23 0 110 0 0
T24 0 6 0 0
T36 0 6 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14131 13973 0 0
T2 242183 242107 0 0
T3 4568 2044 0 0
T4 2228 235 0 0
T5 3457 1865 0 0
T9 76326 75726 0 0
T11 138958 138949 0 0
T12 16136 16058 0 0
T13 166534 164501 0 0
T14 187095 187085 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2272701 0 0
T1 14131 102 0 0
T2 242183 0 0 0
T3 4568 2361 0 0
T4 2228 1837 0 0
T5 3457 1442 0 0
T7 0 142700 0 0
T8 0 213708 0 0
T9 76326 534 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 1979 0 0
T14 187095 0 0 0
T15 0 3636 0 0
T19 0 6397 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7556 0 0
T1 14131 2 0 0
T2 242183 0 0 0
T3 4568 1 0 0
T4 2228 1 0 0
T5 3457 0 0 0
T9 76326 10 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 9 0 0
T14 187095 0 0 0
T15 0 18 0 0
T19 0 46 0 0
T23 0 110 0 0
T24 0 6 0 0
T36 0 6 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7556 0 0
T1 14131 2 0 0
T2 242183 0 0 0
T3 4568 1 0 0
T4 2228 1 0 0
T5 3457 0 0 0
T9 76326 10 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 9 0 0
T14 187095 0 0 0
T15 0 18 0 0
T19 0 46 0 0
T23 0 110 0 0
T24 0 6 0 0
T36 0 6 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2272701 0 0
T1 14131 102 0 0
T2 242183 0 0 0
T3 4568 2361 0 0
T4 2228 1837 0 0
T5 3457 1442 0 0
T7 0 142700 0 0
T8 0 213708 0 0
T9 76326 534 0 0
T11 138958 0 0 0
T12 16136 0 0 0
T13 166534 1979 0 0
T14 187095 0 0 0
T15 0 3636 0 0
T19 0 6397 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14131 14075 0 0
T2 242183 242107 0 0
T3 4568 4405 0 0
T4 2228 2072 0 0
T5 3457 3307 0 0
T9 76326 76260 0 0
T11 138958 138949 0 0
T12 16136 16058 0 0
T13 166534 166480 0 0
T14 187095 187085 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%