Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	381704	0	0
entropy_period_rd_A	2147483647	1222	0	0
intr_enable_rd_A	2147483647	2222	0	0
prefix_0_rd_A	2147483647	1444	0	0
prefix_10_rd_A	2147483647	1393	0	0
prefix_1_rd_A	2147483647	1383	0	0
prefix_2_rd_A	2147483647	1279	0	0
prefix_3_rd_A	2147483647	1319	0	0
prefix_4_rd_A	2147483647	1313	0	0
prefix_5_rd_A	2147483647	1396	0	0
prefix_6_rd_A	2147483647	1281	0	0
prefix_7_rd_A	2147483647	1216	0	0
prefix_8_rd_A	2147483647	1386	0	0
prefix_9_rd_A	2147483647	1422	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	381704	0	0
T28	107003	116101	0	0
T32	1584	0	0	0
T47	0	20369	0	0
T48	0	50411	0	0
T118	0	100737	0	0
T119	0	63626	0	0
T120	0	27099	0	0
T121	0	9	0	0
T122	0	22	0	0
T123	0	187	0	0
T124	0	293	0	0
T125	154489	0	0	0
T126	1446	0	0	0
T127	1261	0	0	0
T128	465151	0	0	0
T129	743863	0	0	0
T130	157731	0	0	0
T131	1852	0	0	0
T132	468463	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1222	0	0
T94	13514	45	0	0
T112	26771	118	0	0
T114	22430	110	0	0
T144	6904	29	0	0
T145	8099	10	0	0
T146	2761	7	0	0
T147	45112	216	0	0
T148	2803	20	0	0
T149	8435	19	0	0
T150	5675	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2222	0	0
T94	13514	37	0	0
T112	26771	183	0	0
T114	22430	169	0	0
T116	1278	13	0	0
T144	6904	14	0	0
T145	8099	21	0	0
T146	2761	4	0	0
T151	4941	2	0	0
T152	1572	22	0	0
T153	1229	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1444	0	0
T94	13514	19	0	0
T112	26771	78	0	0
T114	22430	91	0	0
T144	6904	19	0	0
T145	8099	15	0	0
T146	2761	9	0	0
T147	45112	243	0	0
T148	2803	4	0	0
T149	8435	12	0	0
T151	4941	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1393	0	0
T94	13514	30	0	0
T112	26771	86	0	0
T114	22430	68	0	0
T144	6904	22	0	0
T145	8099	23	0	0
T146	2761	8	0	0
T147	45112	280	0	0
T148	2803	12	0	0
T149	8435	13	0	0
T151	4941	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1383	0	0
T94	13514	35	0	0
T112	26771	84	0	0
T114	22430	86	0	0
T144	6904	2	0	0
T145	8099	7	0	0
T146	2761	2	0	0
T147	45112	203	0	0
T148	2803	10	0	0
T149	8435	21	0	0
T151	4941	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1279	0	0
T94	13514	15	0	0
T112	26771	71	0	0
T114	22430	76	0	0
T144	6904	9	0	0
T145	8099	10	0	0
T146	2761	7	0	0
T147	45112	207	0	0
T148	2803	13	0	0
T149	8435	22	0	0
T151	4941	12	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1319	0	0
T94	13514	27	0	0
T112	26771	76	0	0
T114	22430	90	0	0
T144	6904	25	0	0
T145	8099	16	0	0
T147	45112	234	0	0
T148	2803	15	0	0
T149	8435	19	0	0
T150	5675	12	0	0
T151	4941	8	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313	0	0
T94	13514	24	0	0
T112	26771	84	0	0
T114	22430	106	0	0
T144	6904	13	0	0
T145	8099	17	0	0
T147	45112	185	0	0
T148	2803	8	0	0
T149	8435	9	0	0
T150	5675	8	0	0
T151	4941	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T94	13514	30	0	0
T112	26771	82	0	0
T114	22430	70	0	0
T144	6904	25	0	0
T145	8099	21	0	0
T146	2761	7	0	0
T147	45112	177	0	0
T148	2803	7	0	0
T149	8435	26	0	0
T151	4941	24	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1281	0	0
T94	13514	26	0	0
T112	26771	73	0	0
T114	22430	60	0	0
T124	10165	1	0	0
T144	6904	44	0	0
T145	8099	15	0	0
T147	45112	252	0	0
T148	2803	5	0	0
T149	8435	10	0	0
T151	4941	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216	0	0
T94	13514	28	0	0
T112	26771	95	0	0
T114	22430	42	0	0
T144	6904	27	0	0
T145	8099	7	0	0
T146	2761	6	0	0
T147	45112	180	0	0
T148	2803	4	0	0
T149	8435	14	0	0
T151	4941	14	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1386	0	0
T94	13514	24	0	0
T112	26771	76	0	0
T114	22430	90	0	0
T144	6904	6	0	0
T145	8099	21	0	0
T146	2761	7	0	0
T147	45112	253	0	0
T148	2803	8	0	0
T149	8435	25	0	0
T151	4941	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1422	0	0
T94	13514	50	0	0
T112	26771	91	0	0
T114	22430	87	0	0
T144	6904	27	0	0
T145	8099	17	0	0
T146	2761	6	0	0
T147	45112	223	0	0
T148	2803	10	0	0
T149	8435	11	0	0
T151	4941	14	0	0