Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	251177980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198867533

1

T1

136194

T2

811

T3

92581

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	237436098	1			T1	38783		T2	935		T3	98403
values[0x0]	102155044	1			T1	53303		T2	259		T3	22275
values[0x1]	110454371	1			T1	53707		T2	273		T3	24095

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	195778502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254267011

1

T1

138673

T2

959

T3

104550

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1300845	1			T1	532		T3	41		T13	1665
valid_sources[0x01]	1800096	1			T1	653		T3	32		T13	1711
valid_sources[0x02]	1307214	1			T1	601		T3	23		T13	1638
valid_sources[0x03]	1396538	1			T1	550		T3	29		T13	1614
valid_sources[0x04]	1306569	1			T1	527		T3	45		T13	1652
valid_sources[0x05]	4732637	1			T1	602		T3	33		T20	1
valid_sources[0x06]	1310152	1			T1	602		T3	26		T13	1661
valid_sources[0x07]	1301279	1			T1	627		T3	30		T20	1
valid_sources[0x08]	3818250	1			T1	528		T3	30		T13	1538
valid_sources[0x09]	1313473	1			T1	586		T3	41		T13	1691
valid_sources[0x0a]	1766094	1			T1	547		T3	33		T13	1766
valid_sources[0x0b]	1814069	1			T1	564		T3	35		T13	1531
valid_sources[0x0c]	2630295	1			T1	521		T3	41		T13	1541
valid_sources[0x0d]	2486792	1			T1	614		T3	38		T13	1570
valid_sources[0x0e]	1302815	1			T1	556		T3	32		T13	1642
valid_sources[0x0f]	3494255	1			T1	568		T3	26		T13	1594
valid_sources[0x10]	1303738	1			T1	578		T3	22		T13	1724
valid_sources[0x11]	2821497	1			T1	561		T3	43		T13	1615
valid_sources[0x12]	1307272	1			T1	496		T3	35		T13	1731
valid_sources[0x13]	1319729	1			T1	552		T3	18		T13	1769
valid_sources[0x14]	1299318	1			T1	583		T3	27		T13	1655
valid_sources[0x15]	1309195	1			T1	544		T3	34		T13	1561
valid_sources[0x16]	1500520	1			T1	568		T3	33		T13	1744
valid_sources[0x17]	1307436	1			T1	556		T3	32		T13	1743
valid_sources[0x18]	1308688	1			T1	561		T3	33		T13	1597
valid_sources[0x19]	1311443	1			T1	579		T3	25		T13	1757
valid_sources[0x1a]	1302012	1			T1	518		T3	27		T13	1641
valid_sources[0x1b]	1302272	1			T1	634		T3	35		T13	1619
valid_sources[0x1c]	1306669	1			T1	592		T3	32		T13	1663
valid_sources[0x1d]	1977614	1			T1	561		T3	30		T13	1606
valid_sources[0x1e]	1303647	1			T1	537		T3	32		T13	1675
valid_sources[0x1f]	1481188	1			T1	557		T3	33		T13	1655
valid_sources[0x20]	1420730	1			T1	564		T3	33		T13	1540
valid_sources[0x21]	1307171	1			T1	616		T3	31		T13	1629
valid_sources[0x22]	2205645	1			T1	629		T3	43		T13	1737
valid_sources[0x23]	1347018	1			T1	539		T3	34		T13	1648
valid_sources[0x24]	3732467	1			T1	567		T3	34		T13	1724
valid_sources[0x25]	1306068	1			T1	562		T3	38		T13	1631
valid_sources[0x26]	1311576	1			T1	578		T3	29		T13	1665
valid_sources[0x27]	1775647	1			T1	628		T3	25		T13	1552
valid_sources[0x28]	1303745	1			T1	544		T3	31		T13	1526
valid_sources[0x29]	1303335	1			T1	587		T3	51		T13	1590
valid_sources[0x2a]	1304361	1			T1	560		T3	28		T13	1580
valid_sources[0x2b]	1301976	1			T1	563		T3	27		T13	1694
valid_sources[0x2c]	2420923	1			T1	527		T3	39		T13	1681
valid_sources[0x2d]	1320944	1			T1	590		T3	27		T13	1628
valid_sources[0x2e]	1327775	1			T1	566		T3	28		T13	1544
valid_sources[0x2f]	1437517	1			T1	587		T3	136456		T13	1744
valid_sources[0x30]	1302743	1			T1	587		T3	26		T13	1523
valid_sources[0x31]	1389598	1			T1	541		T3	40		T13	1455
valid_sources[0x32]	1304744	1			T1	554		T3	27		T13	1628
valid_sources[0x33]	1305541	1			T1	570		T3	36		T13	1630
valid_sources[0x34]	1307761	1			T1	608		T2	1466		T3	24
valid_sources[0x35]	1313902	1			T1	530		T3	31		T13	1634
valid_sources[0x36]	1980454	1			T1	573		T3	43		T13	1626
valid_sources[0x37]	1305352	1			T1	573		T3	43		T13	1672
valid_sources[0x38]	1301989	1			T1	575		T3	33		T20	1
valid_sources[0x39]	1305018	1			T1	531		T3	29		T13	1635
valid_sources[0x3a]	1302533	1			T1	597		T3	28		T13	1695
valid_sources[0x3b]	1776300	1			T1	550		T3	29		T13	1620
valid_sources[0x3c]	2442491	1			T1	581		T3	27		T13	1578
valid_sources[0x3d]	1309391	1			T1	542		T3	36		T13	1674
valid_sources[0x3e]	3753920	1			T1	591		T3	29		T13	1669
valid_sources[0x3f]	1304865	1			T1	623		T3	42		T13	1820
valid_sources[0x40]	1421629	1			T1	527		T3	25		T13	1604
valid_sources[0x41]	1307538	1			T1	558		T3	29		T13	1561
valid_sources[0x42]	3708381	1			T1	612		T3	27		T13	1604
valid_sources[0x43]	1302065	1			T1	566		T3	31		T13	1668
valid_sources[0x44]	1324740	1			T1	559		T3	37		T13	1737
valid_sources[0x45]	1299609	1			T1	585		T3	36		T13	1554
valid_sources[0x46]	1440949	1			T1	594		T3	37		T13	1619
valid_sources[0x47]	1302951	1			T1	614		T3	35		T13	1675
valid_sources[0x48]	1302150	1			T1	567		T3	28		T20	1
valid_sources[0x49]	4385136	1			T1	610		T3	37		T13	1629
valid_sources[0x4a]	2154583	1			T1	564		T3	38		T13	1664
valid_sources[0x4b]	1973186	1			T1	554		T3	23		T13	1751
valid_sources[0x4c]	1307235	1			T1	578		T3	29		T20	1
valid_sources[0x4d]	3343830	1			T1	570		T3	32		T13	1673
valid_sources[0x4e]	1308537	1			T1	557		T3	31		T13	1719
valid_sources[0x4f]	1305725	1			T1	515		T3	32		T13	1641
valid_sources[0x50]	1325064	1			T1	580		T3	41		T13	1576
valid_sources[0x51]	2265042	1			T1	574		T3	41		T13	1709
valid_sources[0x52]	1385977	1			T1	644		T3	33		T13	1718
valid_sources[0x53]	1969737	1			T1	535		T3	38		T13	1716
valid_sources[0x54]	1303675	1			T1	578		T3	35		T13	1611
valid_sources[0x55]	1426042	1			T1	579		T3	24		T13	1544
valid_sources[0x56]	1304234	1			T1	577		T3	21		T13	1694
valid_sources[0x57]	1781783	1			T1	574		T2	1		T3	37
valid_sources[0x58]	1339786	1			T1	546		T3	23		T13	1604
valid_sources[0x59]	1303277	1			T1	621		T3	29		T13	1744
valid_sources[0x5a]	3334059	1			T1	578		T3	33		T13	1725
valid_sources[0x5b]	1378887	1			T1	517		T3	40		T20	1
valid_sources[0x5c]	1334569	1			T1	552		T3	26		T13	1553
valid_sources[0x5d]	1308708	1			T1	568		T3	41		T13	1667
valid_sources[0x5e]	2068221	1			T1	546		T3	28		T20	1
valid_sources[0x5f]	1760235	1			T1	517		T3	34		T13	1751
valid_sources[0x60]	2205997	1			T1	563		T3	22		T13	1638
valid_sources[0x61]	1303339	1			T1	543		T3	33		T20	1
valid_sources[0x62]	2206648	1			T1	554		T3	32		T13	1709
valid_sources[0x63]	2091448	1			T1	581		T3	26		T13	1499
valid_sources[0x64]	1306768	1			T1	607		T3	24		T20	2
valid_sources[0x65]	1304093	1			T1	580		T3	36		T13	1599
valid_sources[0x66]	1860121	1			T1	546		T3	29		T13	1591
valid_sources[0x67]	2362339	1			T1	594		T3	26		T13	1514
valid_sources[0x68]	1305564	1			T1	588		T3	25		T13	1644
valid_sources[0x69]	1307439	1			T1	565		T3	18		T13	1583
valid_sources[0x6a]	3432584	1			T1	562		T3	42		T13	1676
valid_sources[0x6b]	1451376	1			T1	569		T3	42		T13	1697
valid_sources[0x6c]	1392070	1			T1	544		T3	31		T13	1627
valid_sources[0x6d]	1299601	1			T1	580		T3	37		T13	1736
valid_sources[0x6e]	1306943	1			T1	579		T3	44		T13	1623
valid_sources[0x6f]	1302966	1			T1	588		T3	25		T13	1621
valid_sources[0x70]	1326963	1			T1	564		T3	49		T20	1
valid_sources[0x71]	2043816	1			T1	560		T3	38		T13	1571
valid_sources[0x72]	1313435	1			T1	584		T3	34		T13	1745
valid_sources[0x73]	1310884	1			T1	575		T3	33		T13	1627
valid_sources[0x74]	1311091	1			T1	592		T3	37		T13	1501
valid_sources[0x75]	3372054	1			T1	571		T3	29		T13	1598
valid_sources[0x76]	1301239	1			T1	512		T3	32		T13	1654
valid_sources[0x77]	2185888	1			T1	566		T3	36		T13	1625
valid_sources[0x78]	1302653	1			T1	579		T3	27		T13	1590
valid_sources[0x79]	1305154	1			T1	531		T3	36		T13	1708
valid_sources[0x7a]	1304986	1			T1	560		T3	43		T13	1670
valid_sources[0x7b]	1308794	1			T1	600		T3	30		T13	1620
valid_sources[0x7c]	2179266	1			T1	512		T3	34		T13	1637
valid_sources[0x7d]	1374789	1			T1	538		T3	30		T13	1625
valid_sources[0x7e]	2418719	1			T1	607		T3	36		T13	1596
valid_sources[0x7f]	3367431	1			T1	536		T3	35		T13	1643
valid_sources[0x80]	2164589	1			T1	558		T3	40		T13	1604

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86818019

1

T1

30576

T2

567

T3

67023

values[0x0]

all_enables

biggest_size

60264965

1

T1

52673

T2

132

T3

13674

values[0x1]

all_enables

biggest_size

51784549

1

T1

52945

T2

112

T3

11884