Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

252999530

1

T1

9599

T2

656

T3

52192

full_word

198982383

1

T1

136194

T2

811

T3

92581

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451981633	1			T1	145793		T2	1467		T3	144773
auto[TlIntgErrCmd]	92	1			T102	4		T103	2		T104	4
auto[TlIntgErrData]	100	1			T102	5		T103	3		T104	3
auto[TlIntgErrBoth]	88	1			T102	1		T103	5		T104	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237788761

1

T1

38783

T2

935

T3

98403

auto[1]

214193152

1

T1

107010

T2

532

T3

46370

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	150941945	1			T1	8207		T2	368		T3	31380
auto[TlIntgErrNone]	partial	auto[1]	102057323	1			T1	1392		T2	288		T3	20812
auto[TlIntgErrNone]	full_word	auto[0]	86846694	1			T1	30576		T2	567		T3	67023
auto[TlIntgErrNone]	full_word	auto[1]	112135671	1			T1	105618		T2	244		T3	25558
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T102	1		T103	1		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T102	3		T103	1		T104	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T169	1		T170	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T172	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T102	2		T103	1		T104	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T102	1		T103	2		T104	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T102	2		T168	1		T169	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T173	1		T174	1		T175	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T102	1		T103	1		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T103	2		T104	2		T167	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T171	1		T176	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T103	2		-	-		-	-